公开(公告)号：US10096691B2

公开(公告)日：2018-10-09

申请号：US14812490

申请日：2015-07-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu Zhang ,  Lichuan Zhao ,  Xiongkun Yang ,  Huaxiang Yin ,  Jiang Yan ,  Junfeng Li ,  Tao Yang ,  Jinbiao Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L29/417 ,  H01L21/28

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

公开(公告)号：US09590076B1

公开(公告)日：2017-03-07

申请号：US14402303

申请日：2014-08-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinbiao Liu ,  Yao Wang ,  Guilei Wang ,  Tao Yang ,  Qing Liu ,  Junfeng Li

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/785

Abstract: A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.

Abstract translation: 一种制造FinFET器件的方法，包括提供衬底; 在衬底上实现源极/漏极掺杂; 蚀刻掺杂衬底以形成源区和漏区; 在源极区域和漏极区域之间形成鳍状沟道; 并在Fin通道上形成一个门。 在源极/漏极掺杂在衬底上实现之后形成鳍和栅极，使得源极/漏极掺杂作为平面器件的掺杂进行，这确保了源/漏极应对的质量并提高了其性能 的FinFET器件。

公开(公告)号：US09331172B2

公开(公告)日：2016-05-03

申请号：US14426690

申请日：2012-11-13

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Lingkuan Meng ,  Xiaobin He ,  Guanglu Chen ,  Chao Zhao

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/51 ,  H01L29/66492 ,  H01L29/66621 ,  H01L29/66833

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract translation: 一种用于制造虚拟栅极结构的方法。 该方法可以包括：顺序地在半导体衬底上形成伪栅极氧化物层和虚拟栅极材料层; 在虚拟栅极材料层上形成ONO结构; 在ONO结构上形成顶部非晶硅层; 在顶部非晶硅层上形成图案化的光致抗蚀剂层; 用图案化的光致抗蚀剂层作为掩模蚀刻顶部非晶硅层，蚀刻停止在ONO结构上; 用图案化的光致抗蚀剂层和顶部非晶硅层的剩余部分作为掩模蚀刻ONO结构，蚀刻停止在虚拟栅极材料层上; 去除图案化的光致抗蚀剂层; 并且蚀刻伪栅极材料层，蚀刻停止在虚设栅极氧化层处以形成虚拟栅极结构。

公开(公告)号：US10115804B2

公开(公告)日：2018-10-30

申请号：US14698624

申请日：2015-04-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei Wang ,  Junfeng Li ,  Jinbiao Liu ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/285 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.

公开(公告)号：US09589809B2

公开(公告)日：2017-03-07

申请号：US14744835

申请日：2015-06-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qiang Xu ,  Chao Zhao ,  Jun Luo ,  Guilei Wang ,  Tao Yang ,  Junfeng Li

IPC: H01L21/28 ,  H01L21/285 ,  C23C16/02 ,  C23C16/14 ,  C23C16/455 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/28562 ,  C23C16/0272 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/76876 ,  H01L21/76877 ,  H01L29/66545

Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.

Abstract translation: 公开了沉积钨（W）层的方法。 一方面，该方法包括在衬底的表面上沉积SiH 4基底W膜以预处理该表面。 该方法包括在预处理的表面上沉积B2H6基底W层。 SiH4基底W膜可以是几个原子层厚。 膜和基底W层可以沉积在单个ALD工艺中，包括反应气体浸泡，反应气体引入和主沉积操作。 形成膜可以包括在气体浸泡操作期间将SiH 4气体引入反应腔中，并且在气体引入操作期间将SiH 4和WF 6气体引入空腔。 SiH4和WF6气体可以根据待沉积的钨层的厚度交替地引入多个循环。

公开(公告)号：US20160379829A1

公开(公告)日：2016-12-29

申请号：US14838628

申请日：2015-08-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei Wang ,  Jinbiao Liu ,  Jianfeng Gao ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/7845

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Abstract translation: 提供一种制造半导体器件的方法，包括：通过去除牺牲栅极提供其上形成有多个开口的半导体衬底; 用具有压应力的顶部金属层填充开口; 并且在PMOS器件区域中相对于顶部金属层执行非晶掺杂。 因此，有可能有效地提高NMOS器件的载流子迁移率，并且还可以降低PMOS器件区域中的压应力，以确保PMOS器件的期望性能。

公开(公告)号：US20140357027A1

公开(公告)日：2014-12-04

申请号：US14364950

申请日：2012-03-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/45 ,  H01L21/84

CPC classification number: H01L21/823814 ,  H01L21/2255 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.

Abstract translation: 本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域 。 根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。

公开(公告)号：US20250006822A1

公开(公告)日：2025-01-02

申请号：US18708028

申请日：2023-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Na Zhou ,  Junjie Li ,  Jianfeng Gao ,  Tao Yang ,  Junfeng Li ,  Jun Luo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.

公开(公告)号：US10312345B2

公开(公告)日：2019-06-04

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan Xiang ,  Xiaolei Wang ,  Hong Yang ,  Shi Liu ,  Junfeng Li ,  Wenwu Wang ,  Chao Zhao

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/265 ,  H01L29/49

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

公开(公告)号：US09773707B2

公开(公告)日：2017-09-26

申请号：US14838628

申请日：2015-08-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei Wang ,  Jinbiao Liu ,  Jianfeng Gao ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215

CPC classification number: H01L21/823828 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/7845

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.