公开(公告)号：US20240266430A1

公开(公告)日：2024-08-08

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long ZHANG ,  Weifeng SUN ,  Siyang LIU ,  Jie MA ,  Peigang LIU ,  Longxing SHI

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US20240257438A1

公开(公告)日：2024-08-01

申请号：US18563997

申请日：2023-04-06

Applicant: Southeast University

Inventor： Chengxiang WANG ,  Jialing HUANG ,  Yingzhuo SUN ,  Jie HUANG ,  Fuchun ZHENG

IPC: G06T15/06

CPC classification number: G06T15/06

Abstract: Disclosed in the present disclosure is a ray tracing channel modeling method for reconfigurable intelligent surface wireless communication. The method comprises: setting an application scene; implementing RIS deployment and adjustment mode; analyzing a received power distribution of a non-line-of-sight scene; analyzing an angle power spectral density; and specifically analyzing the change of a channel capacity with the change of a transmitting power, a RIS unit number and a RIS deployment position. In the present disclosure, a RIS channel deterministic model based on ray tracing can be used for a static ray tracing simulation software, the deployment of any scale of a reconfigurable intelligent surface at any position in a scene is supported, the ray tracing modeling method of the reconfigurable intelligent surface is enriched, and the channel characteristic analysis of the simulation result has guiding significance for the application and deployment of RIS in indoor scenes.

公开(公告)号：US12051742B1

公开(公告)日：2024-07-30

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Jie Ma ,  Peigang Liu ,  Longxing Shi

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US12027516B1

公开(公告)日：2024-07-02

申请号：US18568277

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Weifeng Sun ,  Mengli Liu ,  Yanfeng Ma ,  Longxing Shi

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7787

Abstract: A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

公开(公告)号：US20240094072A1

公开(公告)日：2024-03-21

申请号：US18025186

申请日：2022-05-12

Applicant: SOUTHEAST UNIVERSITY

Inventor： Aiguo SONG ,  Jingjing XU ,  Shuyan YANG ,  Baoguo XU ,  Huijun LI ,  Ruqi MA

IPC: G01L1/18 ,  G01L5/1627

CPC classification number: G01L1/18 ,  G01L5/1627

Abstract: A miniature combined multi-axis force sensor structure includes a sensor body, a first shell and a second shell, two horizontal main beams and two vertical main beams are arranged on the periphery of an inner round platform in a cross shape, tail ends of the horizontal main beams and the vertical main beams are each connected to a vertical floating beam, and the horizontal floating beams consist of two thin-walled cambered beams; two ends of the horizontal floating beam are each connected to an outer round platform by means of an annular platform; the sensor body is arranged between the first shell and the second shell; strain gauges are stuck on the horizontal main beams and the vertical main beams to form two Wheatstone bridges; and when force/torque acts on the cross beam, the sensor deforms, and the resistance value of strain gauge at corresponding position changes.

公开(公告)号：US20240084463A1

公开(公告)日：2024-03-14

申请号：US18550629

申请日：2023-01-04

Applicant: SOUTHEAST UNIVERSITY

Inventor： Rui XIAO ,  Chao LIU ,  Tao LI ,  Weicong XU ,  Peijun LI ,  Feng GONG

IPC: C25B3/26 ,  C25B15/08

CPC classification number: C25B3/26 ,  C25B15/087

Abstract: A system and method for CO2 capture and electroregeneration and synchronous conversion are provided. The system includes a CO2 capture subsystem, which uses an absorption liquid to capture CO2 and generate a capture liquid; and a CO2 electroregeneration and synchronous conversion subsystem, including a cathode chamber provided with a cathode electrode, a sample inlet, and a sample outlet, an anode chamber having an anode electrode, a sample inlet connected to an outlet of the capture liquid of the CO2 capture subsystem, and a sample outlet connected to the sample inlet of the cathode chamber for introducing CO2 regenerated by anodic oxidation into the cathode chamber for electroreduction, and a balance chamber in the middle having a sample outlet connected to an inlet of the absorption liquid of the CO2 capture subsystem. The system can perform self-circulation and stably operate, to capture, regenerate and convert CO2.

公开(公告)号：US11929624B2

公开(公告)日：2024-03-12

申请号：US17639439

申请日：2021-06-23

Applicant: SOUTHEAST UNIVERSITY

Inventor： Wu Chen ,  Guohao He

IPC: H02J3/46 ,  H02M5/458

CPC classification number: H02J3/46 ,  H02M5/4585 ,  H02J2203/10

Abstract: The invention discloses a power network flexible controller topology shared by modules. Each single-phase topology comprises an AC/AC converter including N1 CHB modules, and an AC/DC module including N−N1 full-bridge rectifiers; the AC input terminals of N1 CHB modules are connected in series to form an AC port on one side of the AC/AC converter, the AC output terminals of N1 CHB modules are connected in series to form the AC port on the other side of the AC/AC converter, the AC input terminals of N−N1 full-bridge rectifiers are connected in series to form the AC port of the AC/DC module, the AC port on one side of the AC/AC converter is connected in series with the AC side port of the AC/DC module and then connected to a first AC network nd the AC port on the other side of the AC/AC converter is connected in series with the DC side port of the AC/DC module.

公开(公告)号：US11911536B2

公开(公告)日：2024-02-27

申请号：US17602202

申请日：2020-09-23

Applicant: SOUTHEAST UNIVERSITY

Inventor： Ning Gu ,  Xin Liu

IPC: A61L31/00 ,  A61L31/04 ,  B29C39/38 ,  B29L31/00

CPC classification number: A61L31/047 ,  B29C39/38 ,  B29K2089/00 ,  B29L2031/7542

Abstract: The present invention relates to a method for molding a self-supporting silk fibroin catheter stent, which comprises preparing an excellent catheter stent by a mold casting and freeze-drying molding process using silk fibroin as a raw material. The raw material is silk fibroin extracted from natural mulberry silk; and the mold is a hollow tubular mold, having an outer shell that is a transparent polyethylene straw with a diameter of 6 mm and an inner core that is a fiber rod FRP with a diameter of 3 mm, with the two ends being closed. The mold casting and freeze-drying molding process comprises the steps of casting; pre-freezing; removing the mold and placing the mold onto a pre-frozen freeze-drying plate; and freeze-drying. The freeze-drying procedure comprises: (1) a pre-freezing stage; (2) a freezing-vacuum transition stage; (3) a gradient temperature-rising and freeze-drying stage; and (4) a secondary freeze-drying stage. The freeze-drying procedure is strictly regulated in accordance with the specifications of freeze-dried stents. The prepared stent has a good shape, and good tolerance without adding any additional components. The stent presents a three-dimensional porous space structure, the process is simple, and the stent meets the requirements for tissue-engineered vascular stent in clinic.

公开(公告)号：US11894458B2

公开(公告)日：2024-02-06

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing Wei ,  Qichao Wang ,  Kui Xiao ,  Dejin Wang ,  Li Lu ,  Ling Yang ,  Ran Ye ,  Siyang Liu ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/78

CPC classification number: H01L29/7825

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US11790142B2

公开(公告)日：2023-10-17

申请号：US18014002

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Haiyang Jiang ,  Jiahao Wang

IPC: G06F30/3312 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/3315 ,  G06F2119/12

Abstract: Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.