公开(公告)号：US10340906B2

公开(公告)日：2019-07-02

申请号：US15779432

申请日：2017-01-23

Applicant: SOUTHEAST UNIVERSITY ,  SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE

Inventor： Weifeng Sun ,  Yunwu Zhang ,  Kuo Yu ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H02M3/07 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185 ,  H01L27/07 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

公开(公告)号：US12224340B2

公开(公告)日：2025-02-11

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang Liu ,  Chi Zhang ,  Kui Xiao ,  Guipeng Sun ,  Dejin Wang ,  Jiaxing Wei ,  Li Lu ,  Weifeng Sun ,  Shengli Lu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US11322606B2

公开(公告)日：2022-05-03

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Xinyi Tao ,  Ningbo Li ,  Longxing Shi

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US09159818B2

公开(公告)日：2015-10-13

申请号：US14349632

申请日：2012-10-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC: H01L27/24 ,  H01L29/739 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

公开(公告)号：US20140203406A1

公开(公告)日：2014-07-24

申请号：US14240287

申请日：2012-08-14

Applicant: SOUTHEAST UNIVERSITY

Inventor： Longxing Shi ,  Qinsong Qian ,  Weifeng Sun ,  Jing Zhu ,  Xianguo Huang ,  Shengli Lu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/761

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L21/823481 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Abstract translation: 高电压驱动电路的隔离结构包括P型衬底和P型外延层; 在P型外延层上布置有高电压区域，低电压区域和高低压端子区域; 在高低压区和低电压区之间设置第一P型结隔离区，高电压区与低压区之间设置高压绝缘栅场效应管; 高压绝缘栅场效应管的两侧和高压绝缘栅场效应管与高边区之间的隔离结构形成为第二P型结隔离区。

公开(公告)号：US12183818B2

公开(公告)日：2024-12-31

申请号：US17417677

申请日：2019-12-23

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng Sun ,  Rongcheng Lou ,  Kui Xiao ,  Feng Lin ,  Jiaxing Wei ,  Sheng Li ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

公开(公告)号：US12051742B1

公开(公告)日：2024-07-30

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Jie Ma ,  Peigang Liu ,  Longxing Shi

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US12027516B1

公开(公告)日：2024-07-02

申请号：US18568277

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Weifeng Sun ,  Mengli Liu ,  Yanfeng Ma ,  Longxing Shi

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7787

Abstract: A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

公开(公告)号：US11894458B2

公开(公告)日：2024-02-06

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing Wei ,  Qichao Wang ,  Kui Xiao ,  Dejin Wang ,  Li Lu ,  Ling Yang ,  Ran Ye ,  Siyang Liu ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/78

CPC classification number: H01L29/7825

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US11515395B2

公开(公告)日：2022-11-29

申请号：US17624336

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Siyang Liu ,  Ningbo Li ,  Dejin Wang ,  Kui Xiao ,  Chi Zhang ,  Sheng Li ,  Xinyi Tao ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/861

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.