Common data path rake receiver for cdma demodulator circuit
    93.
    发明专利
    Common data path rake receiver for cdma demodulator circuit 审中-公开
    CDMA解调器电路的通用数据路径接收机

    公开(公告)号:JP2003332945A

    公开(公告)日:2003-11-21

    申请号:JP2003129280

    申请日:2003-05-07

    Inventor: CERVINI STEFANO

    CPC classification number: H04B1/7115 H04B2201/70707

    Abstract: PROBLEM TO BE SOLVED: To improve a rake receiver used when spread-spectrum signal is demodulated.
    SOLUTION: An architecture for a rake receiver of a CDMA demodulator utilizes a common data path for signal processing. This common data bus is shared by all channels (either physical channels or propagation paths within physical channels) to avoid redundant calculations, reduce circuit space, and reduce power consumption. The sharing of the common data path for demodulation is made in a time division manner, with each channel being given sequential access to the data bus to perform all or part of a given function (for example, de-scramble, de-spreading, de-rotating, and de-skewing accumulation).
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题:改进扩频信号解调时使用的耙式接收机。 解决方案:用于CDMA解调器的瑞克接收机的架构利用公共数据路径进行信号处理。 该公共数据总线由所有通道(物理通道中的物理通道或传播路径)共享,以避免冗余计算,减少电路空间并降低功耗。 以时分方式共享用于解调的公共数据路径,其中每个信道被给予对数据总线的顺序访问以执行给定功能的全部或部分(例如,去加扰,解扩,de 旋转和反倾销积累)。 版权所有(C)2004,JPO

    Method and system for 3d smoothing within bound of error region of matching curve
    94.
    发明专利
    Method and system for 3d smoothing within bound of error region of matching curve 审中-公开
    用于匹配曲线的错误区域中的3D平滑的方法和系统

    公开(公告)号:JP2003317117A

    公开(公告)日:2003-11-07

    申请号:JP2003114254

    申请日:2003-04-18

    Inventor: NG KIM CHAI

    CPC classification number: G06K9/20 G06K2209/40 G06T7/55

    Abstract: PROBLEM TO BE SOLVED: To provide an improved image processing system and a method to remove and smooth out irregularities from a 3D image representation from multiple 2D image views. SOLUTION: The image processing system and the method are provided to remove and smooth out irregularities from 3D image information reproduced from one scene, specially, multiple 2D image views from a uniform surface of an object in the scene. In this method, a window that overlaps a plurality of pixels of one of a plurality of 2D image views of a scene is defined. Each pixel is associated with predefined 3D depth information and further associated with a matching curve. A subject pixel is located within the plurality of pixels overlapped by the window. An average 3D depth information associated with the plurality of pixels overlapped by the window is calculated and if the calculated average 3D depth information is within an error region of the matching curve associated with the subject pixel, the calculated average 3D depth information is assigned to the 3D depth information of the subject pixel. COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题:提供一种改进的图像处理系统和从多个2D图像视图中去除和平滑来自3D图像表示的不规则的方法。

    解决方案:提供图像处理系统和方法,以从一个场景再现的3D图像信息中去除和平滑不规则,特别是来自场景中物体的均匀表面的多个2D图像视图。 在该方法中,定义与场景的多个2D图像视图中的一个的多个像素重叠的窗口。 每个像素与预定义的3D深度信息相关联并且还与匹配曲线相关联。 被摄体像素位于由窗口重叠的多个像素内。 计算与窗口重叠的多个像素相关联的平均3D深度信息,并且如果所计算的平均3D深度信息在与对象像素相关联的匹配曲线的误差区域内,则将计算出的平均3D深度信息分配给 主体像素的3D深度信息。 版权所有(C)2004,JPO

    Branch fetch architecture for reducing branch penalty without branch prediction
    95.
    发明专利
    Branch fetch architecture for reducing branch penalty without branch prediction 审中-公开
    用于减少分支预算的分支机构的分支机构架构

    公开(公告)号:JP2003058366A

    公开(公告)日:2003-02-28

    申请号:JP2002219623

    申请日:2002-07-29

    CPC classification number: G06F9/3804 G06F9/3842

    Abstract: PROBLEM TO BE SOLVED: To provide new fetch branch architecture for reducing branch penalty without branch prediction.
    SOLUTION: In lieu of the branch prediction, a merged fetch-branch unit operates in parallel with a decode unit in a processor. Upon detection of a branch instruction within a group of one or more fetched instructions, any instructions preceding the branch are marked as regular instructions, the branch instruction is marked as such and any instructions following the branch are marked as sequential instructions. Within two cycles, sequential instructions following the last fetched instruction are retrieved and marked, target instructions beginning at the branch target address are retrieved and marked and the branch is resolved. Either the sequential or target instructions are then dropped depending on the branch resolution, incurring a fixed, 1 cycle branch penalty.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题:提供新的提取分支体系结构,以减少分支损失,无需分支预测。 解决方案:代替分支预测,合并的分支单元与处理器中的解码单元并行操作。 一旦检测到一个或多个获取的指令的组内的分支指令,分支之前的任何指令被标记为常规指令,则分支指令被标记为这样,并且分支之后的任何指令被标记为顺序指令。 在两个周期内,检索并标记最后取出的指令之后的顺序指令,检索并标记在分支目标地址处开始的目标指令,并解析分支。 然后根据分支分辨率,顺序或目标指令被丢弃,产生固定的1个循环分支罚分。

    Circuit and method for detecting servo wedge on spin-up of data-storage disk
    96.
    发明专利
    Circuit and method for detecting servo wedge on spin-up of data-storage disk 审中-公开
    用于检测数据存储盘旋转时的伺服电路的电路和方法

    公开(公告)号:JP2003051166A

    公开(公告)日:2003-02-21

    申请号:JP2002186323

    申请日:2002-06-26

    Inventor: OZDEMIR HAKAN

    CPC classification number: G11B5/59633 G11B19/20 G11B19/28

    Abstract: PROBLEM TO BE SOLVED: To provide an improved servo circuit and a method for detecting a servo wedge on the spin-up of a data storage disk.
    SOLUTION: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. The processor detects one of the servo wedges on spin up of the disk, i.e., while the disk is attaining or after the disk attains an operating speed. By detecting a servo wedge instead of a spin-up wedge to determine an initial head position on disk spin up, such a servo circuit allows one to increase the disk's storage capacity by reducing the number of, or altogether eliminating, spin-up servo wedges from the disk.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题:提供一种改进的伺服电路和用于在数据存储盘的旋转上检测伺服楔的方法。 解决方案:伺服电路包括伺服通道和处理器。 伺服通道从数据存储盘上识别相应数据扇区的伺服楔恢复伺服数据。 处理器检测到在盘旋转时的伺服楔形中的一个,即在盘达到或在盘达到操作速度之后。 通过检测伺服楔而不是旋转楔以确定磁盘上升的初始磁头位置,这样的伺服电路允许通过减少旋转伺服楔的数量或完全消除磁盘的存储容量来增加磁盘的存储容量 从磁盘。

    Circuit and method for temperature detection
    97.
    发明专利
    Circuit and method for temperature detection 审中-公开
    用于温度检测的电路和方法

    公开(公告)号:JP2003004547A

    公开(公告)日:2003-01-08

    申请号:JP2002159882

    申请日:2002-05-31

    Inventor: YIN RONG

    CPC classification number: G01K7/203 G01K15/00

    Abstract: PROBLEM TO BE SOLVED: To provide a device and a method capable of detecting temperature precisely.
    SOLUTION: An illustrative embodiment of this invention has a first oscillator circuit which generates a first signal having a frequency depending on a temperature detected. A differential circuit determines the difference in frequencies between the first signal and a second signal having a frequency which is substantially independent of the temperature, and generates a differential signal having a pulse number based on the difference. A counter circuit, in response to this differential circuit, offsets a predetermined temperature level based on the pulse appeared on the differential signal in order to gain an output signal representing a temperature detected.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题:提供能够精确地检测温度的装置和方法。 解决方案:本发明的说明性实施例具有第一振荡器电路,其产生具有取决于检测到的温度的频率的第一信号。 差分电路确定第一信号和具有基本上与温度无关的频率的第二信号之间的频率差,并且基于该差产生具有脉冲数的差分信号。 响应于该差分电路的计数器电路基于差分信号上出现的脉冲来补偿预定的温度水平,以便获得表示所检测的温度的输出信号。

    Adaptive semiconductor processing using feedback from measurement device
    100.
    发明专利
    Adaptive semiconductor processing using feedback from measurement device 审中-公开
    使用来自测量装置的反馈的自适应半导体处理

    公开(公告)号:JP2014060389A

    公开(公告)日:2014-04-03

    申请号:JP2013171445

    申请日:2013-08-21

    Inventor: ZHANG JOHN H

    CPC classification number: B24B7/228 B24B37/005 B24B49/04 B24B49/105

    Abstract: PROBLEM TO BE SOLVED: To provide an improved semiconductor processing method and device.SOLUTION: The method may include measuring at least one property of a semiconductor wafer and determining a procedure for processing the semiconductor wafer on the basis of the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules on the basis of the determined procedure, and the procedure includes a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an in-line measurement device. The procedure and various parameters associated with the procedure may be determined by a controller of the semiconductor processing device.

    Abstract translation: 要解决的问题:提供一种改进的半导体处理方法和装置。解决方案:该方法可以包括测量半导体晶片的至少一个性质并且基于该至少一个特性确定用于处理半导体晶片的过程。 可以基于确定的过程用多个化学机械抛光(CMP)模块来处理半导体晶片,并且该过程包括用于多个CMP模块中的每一个的至少一个参数的值。 测量可以在原位或通过在线测量装置进行。 与该过程相关的过程和各种参数可以由半导体处理装置的控制器确定。

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