公开(公告)号：WO2005034211A2

公开(公告)日：2005-04-14

申请号：PCT/US2004/032171

申请日：2004-09-30

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  KULP, John, M.

Inventor： KULP, John, M.

IPC: H01L21/00

CPC classification number: G03F7/322

Abstract: A method and apparatus for developing a resist on a substrate in which a sacrificial surfactant-containing liquid is first applied to a resist as a pretreatment to reduce developing process defects and to improve the development process time and the uniformity of the resist. The pretreatment is followed by supplying a developing solution to the resist and thereafter developing the resist.

Abstract translation: 一种用于在基板上显影抗蚀剂的方法和装置，其中先将含牺牲表面活性剂的液体施加到抗蚀剂上作为预处理，以减少显影工艺缺陷并改善显影处理时间和抗蚀剂的均匀性。 预处理之后，向抗蚀剂供给显影液，然后显影抗蚀剂。

公开(公告)号：WO2012129209A2

公开(公告)日：2012-09-27

申请号：PCT/US2012/029767

申请日：2012-03-20

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  LUONG, Vinh, Hoang ,  KO, Akiteru

Inventor： LUONG, Vinh, Hoang ,  KO, Akiteru

IPC: H01L21/66 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: A method of patterning a multi-layer mask (150, 150', 220) is described. The method includes preparing a multi-layer mask (150, 150', 220) on a substrate (1 10, 1 10', 200), wherein the multi-layer mask (150, 150', 220) includes a lithographic layer (226) and an intermediate mask layer (222) underlying the lithographic layer (226), and wherein the intermediate mask layer (222) comprises a carbon-containing compound. The method further includes: establishing an etch process recipe for transferring a pattern (230), that is formed in the lithographic layer (226) and characterized by an initial pattern critical dimension (CD) (152, 152', 232, 232'), to the intermediate mask layer (222); establishing at least one parametric relationship between an intermediate pattern CD (154, 154', 252, 252', 262, 262', 272, 272') to be formed in the intermediate mask layer (222) and at least one process parameter, wherein the at least one parametric relationship provides process conditions capable of increasing and decreasing the initial pattern CD (152, 152', 232, 232') to the intermediate pattern CD (154, 154', 252, 252', 262, 262', 272, 272'); selecting a target process condition to achieve a target CD adjustment between the initial pattern CD (152, 152', 232, 232') and the intermediate pattern CD (154, 154', 252, 252', 262, 262', 272, 272'); and transferring the pattern from the lithographic layer (226) to the intermediate mask layer (222) using the target process condition.

Abstract translation: 描述图案化多层掩模（150,150'，220）的方法。 该方法包括在衬底（110,110'，200）上制备多层掩模（150,150'，220），其中多层掩模（150,150'，220）包括平版印刷层 226）和位于所述光刻层（226）下方的中间掩模层（222），并且其中所述中间掩模层（222）包含含碳化合物。 该方法进一步包括：建立用于转印形成在光刻层（226）中并且由初始图案临界尺寸（CD）（152,152'，232,232'）表征的图案（230）的蚀刻工艺配方 ，到中间掩模层（222）; 建立要在中间掩模层（222）中形成的中间图案CD（154,154'，252,252'，262,262'，272,272'）与至少一个工艺参数之间的至少一个参数关系， 其中所述至少一个参数关系提供能够增加和减少初始图案CD（152,152'，232,232'）到中间图案CD（154,154'，252,252'，262,262'）的处理条件， ，272,272'）; 选择目标处理条件以实现初始图案CD（152,152'，232,232'）与中间图案CD（154,154'，252,252'，262,262'，272,232'）之间的目标CD调整。 272' ）; 并使用目标处理条件将图案从光刻层（226）转印到中间掩模层（222）。

公开(公告)号：WO2012122064A1

公开(公告)日：2012-09-13

申请号：PCT/US2012/027632

申请日：2012-03-03

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  NISHIZUKA, Tetsuya

Inventor： NISHIZUKA, Tetsuya

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/31116 ,  H01L21/31144

Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern. The method includes providing a film stack on a substrate, the film stack containing a SiN film on the substrate and a mask pattern on the SiN film, transferring the mask pattern to the SiN film by exposing the film stack to a first plasma containing a carbon-fluorine-containing gas, O 2 gas, and optionally HBr gas, and exposing the film stack to a second plasma containing a carbon-fluorine- containing gas, O 2 gas, a silicon-fluorine-containing gas, and optionally HBr gas.

Abstract translation: 提供了用掩模图案覆盖的氮化硅（SiN）膜中的等离子体蚀刻特征的处理方法。 该方法包括在基片上提供薄膜叠层，薄膜叠层在基片上含有SiN薄膜和SiN薄膜上的掩模图案，通过将薄膜叠层暴露于含有碳的第一等离子体将掩模图形转移到SiN薄膜 含氟气体，O 2气体和任选的HBr气体，并将膜堆叠暴露于含有含碳氟气体，O 2气体，含硅氟气体和任选的HBr气体的第二等离子体。

公开(公告)号：WO2012071193A2

公开(公告)日：2012-05-31

申请号：PCT/US2011/060386

申请日：2011-11-11

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  DUNN, Shannon, W. ,  HETZER, Dave

Inventor： DUNN, Shannon, W. ,  HETZER, Dave

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  G03F7/0035 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0274 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24479 ,  Y10T428/24612

Abstract: A method for double patterning a substrate (110, 310) is described. The double patterning method may include a litho/freeze/litho/etch (LFLE) technique that includes a first (critical dimension) CD slimming process to reduce the first CD (124, 325) to a first reduced CD (126, 326) and a second CD slimming process to reduce the second CD (144, 326) to a second reduced CD (146, 335).

Abstract translation: 描述了用于双重图案化衬底（110,310）的方法。 双重图案化方法可以包括光刻/冷冻/光刻/蚀刻（LFLE）技术，其包括将第一CD（124,325）还原成第一还原CD（126,326）的第一（临界尺寸）CD纤细过程和 进行第二次CD减肥处理以将第二CD（144,326）减少为第二减少的CD（146,335）。

公开(公告)号：WO2012061232A2

公开(公告)日：2012-05-10

申请号：PCT/US2011/058283

申请日：2011-10-28

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  TAKABA, Hiroyuki

Inventor： TAKABA, Hiroyuki

IPC: H01L21/314

CPC classification number: H01L21/02118 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274

Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.

Abstract translation: 本发明的实施例描述了一种用于形成半导体器件的介电膜的方法。 该方法包括在包含微波等离子体源的处理室中提供衬底，将包含具有碳 - 氮分子间键合的沉积气体的含非金属的处理气体引入处理室，由处理气体形成等离子体，以及 将衬底暴露于等离子体以在衬底上沉积含碳氮膜。 在一些实施例中，含碳氮膜可以包括CN膜，CNO膜，Si掺杂CN膜或Si掺杂CNO膜。

公开(公告)号：WO2012024178A3

公开(公告)日：2012-04-05

申请号：PCT/US2011047541

申请日：2011-08-12

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  METZ ANDREW W

Inventor： METZ ANDREW W

IPC: G03F7/00 ,  G03F7/38

CPC classification number: G03F7/38 ,  G03F7/0035 ,  H01L21/0271 ,  H01L21/0273

Abstract: A method of patterning a substrate (110) is described. The method includes preparing a film stack on a substrate (110), wherein the film stack comprises a spin-on layer (120), and heating the spin-on layer (120) to a cure temperature less than a thermal decomposition temperature of the spin-on layer (120) and exceeding about 200 degrees C to increase mechanical strength of the spin-on layer (120). The method further includes forming a feature pattern (105) without pattern collapse in the spin-on layer (120), wherein the feature pattern (105) is characterized by a critical dimension (155) less than 35nm (nanometers) and an aspect ratio relating a height (150) of the feature pattern (1 05) to the critical dimension (155) exceeding 5:1.

Abstract translation: 描述了图案化衬底（110）的方法。 该方法包括在基底（110）上制备薄膜叠层，其中薄膜叠层包括旋涂层（120），并将旋涂层（120）加热到固化温度小于 旋转层（120）并且超过约200℃以增加旋涂层（120）的机械强度。 该方法还包括在旋涂层（120）中形成无图案折叠的特征图案（105），其中特征图案（105）的特征在于小于35nm（纳米）的临界尺寸（155）和宽高比 将特征图案（105）的高度（150）与超过5:1的临界尺寸（155）相关联。

公开(公告)号：WO2008042695A3

公开(公告)日：2008-10-16

申请号：PCT/US2007079681

申请日：2007-09-27

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  CLARK ROBERT D

Inventor： CLARK ROBERT D

IPC: H01L21/314 ,  H01L29/51

CPC classification number: H01L21/3142 ,  C23C16/308 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45542 ,  H01L21/28202 ,  H01L21/3145 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/945

Abstract: A semiconductor device containing a substrate (25, 92) and a nitrided high-k film (96) on the substrate (25, 92), and method of forming a nitrided high-k film (96). The nitrided high-k film (96) contains an oxygen-containing film and a nitrogen- containing film that is oxidized through at least a portion of the thickness thereof. The nitrogen-containing film and the oxygen-containing film contain the same one or more metal elements selected from alkaline earth elements, rare earth elements, and Group IVB elements of the Periodic Table. The nitrided high-k film (96) can optionally further contain aluminum, siiicon, or aluminum and silicon. The nitrided high-k film (96) is formed on the substrate (25, 92) by a) depositing a nitrogen-containing film, and b) depositing an oxygen-containing film, wherein steps a) and b) are performed in any order, any number of times, so as to oxidize at least a portion of the thickness of the nitrogen-containing film. According to one embodiment, the method includes forming a nitrided hafnium based high-k film (96).

Abstract translation: 一种在衬底（25,92）上包含衬底（25,92）和氮化高k膜（96）的半导体器件以及形成氮化高k膜（96）的方法。 氮化的高k膜（96）包含含氧膜和通过其至少一部分厚度被氧化的含氮膜。 含氮膜和含氧膜含有选自周期表的碱土元素，稀土元素和IVB族元素的相同的一种或多种金属元素。 氮化的高k膜（96）可以可选地进一步包含铝，硅，或铝和硅。 通过以下步骤在衬底（25,92）上形成氮化的高k膜（96）：a）沉积含氮膜，和b）沉积含氧膜，其中步骤a）和b）在任何 任意次数，以便氧化含氮膜的至少一部分厚度。 根据一个实施例，该方法包括形成氮化的基于铪的高k膜（96）。

公开(公告)号：WO2008036496A1

公开(公告)日：2008-03-27

申请号：PCT/US2007/077166

申请日：2007-08-30

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  DUNN, Shannon, W.

Inventor： DUNN, Shannon, W.

IPC: H01L21/027 ,  G03F7/00 ,  G03F7/09 ,  G03F7/095

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/0338

Abstract: A method for double patterning a thin film (220) on a substrate (210) is described. The method includes forming the thin film (220) to be patterned on the substrate (210), forming a developable anti-reflective coating (ARC) layer (240) on the thin film (220), and forming a layer of photo-resist (250) on the arc layer (240). Thereafter, the layer of photo-resist (250) and the arc layer (240) are imaged with a first image pattern region (252), and developed, thus forming the first image pattern (242) in the arc layer (240). The photo-resist (250) is removed and another layer of photo-resist (260) is formed on the arc layer (240). Thereafter, the other layer of photo-resist (260) and the arc layer (240) are imaged with a second image pattern region (254), and developed, thus forming the second image pattern (244) in the arc layer (240). The other photo-resist layer (260) is removed and a double patterned arc layer (240) remains for etching the underlying thin film (220).

Abstract translation: 描述了在衬底（210）上双重图案化薄膜（220）的方法。 该方法包括在衬底（210）上形成待图案化的薄膜（220），在薄膜（220）上形成可显影的抗反射涂层（ARC）层（240），并形成一层光致抗蚀剂 （250）在弧形层（240）上。 此后，用第一图案图案区域（252）对光致抗蚀剂层（250）和电弧层（240）进行成像，并显影，从而在电弧层（240）中形成第一图像图案（242）。 去除光致抗蚀剂（250），在电弧层（240）上形成另一层光致抗蚀剂（260）。 此后，另一层光致抗蚀剂（260）和电弧层（240）用第二图像图案区域（254）成像，并显影，从而在电弧层（240）中形成第二图像图案（244） 。 去除另一光致抗蚀剂层（260），并且留下双层图案化的电弧层（240）以蚀刻下面的薄膜（220）。

公开(公告)号：WO2008021654A2

公开(公告)日：2008-02-21

申请号：PCT/US2007073972

申请日：2007-07-20

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  TAKAHASHI HIROYUKI

Inventor： TAKAHASHI HIROYUKI

CPC classification number: H01L21/67069 ,  H01J37/32844 ,  Y02C20/30 ,  Y02P70/605

Abstract: An exhaust assembly is described for use in a plasma processing system (10, 100, 110, 200, 300, 500, 600, 700), whereby secondary plasma is formed in the exhaust assembly (140, 240, 334) between the processing space and chamber exhaust ports in order to reduce plasma leakage (18) to a vacuum pumping system (16, 130, 330), or improve the uniformity of the processing plasma, or both. The exhaust assembly (140, 240, 334) includes a powered exhaust plate (142, 242) in combination with a ground electrode (244) is utilized to form the secondary plasma surrounding a peripheral edge of a substrate treated in the plasma processing system.

Abstract translation: 描述了用于等离子体处理系统（10,100,110,200,300,500,600,700）中的排气组件，其中在排气组件（140,240,334）中的处理空间之间形成二次等离子体 和腔室排气口，以便将等离子体泄漏（18）减少到真空泵送系统（16,130,330），或改善加工等离子体的均匀性，或者两者。 排气组件（140,240,334）包括与接地电极（244）组合的动力排气板（142,242）用于形成围绕在等离子体处理系统中处理的衬底的周边边缘的次级等离子体。

公开(公告)号：WO2008021598A1

公开(公告)日：2008-02-21

申请号：PCT/US2007/068474

申请日：2007-05-08

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  DIP, Anthony ,  ASARI, Shinji ,  GANDHI, Meenakshisundaram

Inventor： DIP, Anthony ,  ASARI, Shinji ,  GANDHI, Meenakshisundaram

IPC: H01L21/00

CPC classification number: H01L21/67109 ,  C23C16/45578 ,  C23C16/45591 ,  H01L21/67098 ,  H01L21/67103 ,  H01L21/67115

Abstract: A thermal processing system (10) with improved gas flow and method for injecting a process gas into a thermal processing system (10). The thermal processing system (10) has an injection section (50; 82) with injection outlets (52) that inject process gas into a processing space (14) and a delivery section (46; 81; 104) that delivers process gas to the injection section (50). The delivery section (46; 81; 104) may be coupled with the injection section (50; 82) at an inlet disposed between opposite ends (53, 53) of the injection section (50; 82). A fluid lumen (56) of the injection section (50; 82) may have a larger cross-sectional area than a fluid lumen (45) of the delivery section (46; 81; 104). The thermal processing system (10) may include an inner tube (12), which surrounds the processing space (14), having a slit (16) through which the processing space (14) communicates with an annular pumping space (72) defined between the inner tube (12) and an outer tube (12) of the thermal processing system (10).

Abstract translation: 一种具有改善的气流的热处理系统（10）和将工艺气体注入热处理系统（10）的方法。 热处理系统（10）具有注射部分（50; 82），其具有注入口（52），其将处理气体注入处理空间（14）和输送部分（46; 81; 104），其将处理气体输送到 注射部分（50）。 输送部分（46; 81; 104）可以在设置在喷射部分（50; 82）的相对端（53,53）之间的入口处与喷射部分（50; 82）联接。 注射部分（50; 82）的流体腔（56）可以具有比输送部分（46; 81; 104）的流体腔（45）更大的横截面面积。 热处理系统（10）可以包括围绕处理空间（14）的内管（12），其具有狭缝（16），处理空间（14）通过其与环形泵送空间（72）连通， 内管（12）和热处理系统（10）的外管（12）。