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公开(公告)号：KR1020100003590A
公开(公告)日：2010-01-11
申请号：KR1020080063562
申请日：2008-07-01
Applicant: 삼성전자주식회사
IPC: H01L21/3205
CPC classification number: H01L21/76897 , H01L21/76829 , H01L21/76877 , H01L21/823475
Abstract: PURPOSE: A method for manufacturing a stack semiconductor device and the stack semiconductor device manufactured by the same are provided to simplify a process step by forming a contact plug and an external wire at the same time. CONSTITUTION: At least one first transistor is arranged on a first substrate(100). A first source region and a first drain region(106) are arranged on both sides of the first transistor. A lower side of a first contact plug(1510) is contacted with the first source region and the first drain region. A second substrate(200) is arranged on a first substrate. An upper side of at least one second contact plug(1520) is connected to the external wiring. The upper side of the first contact plug and the upper side of the second substrate are positioned on the same plane. A first interlayer insulation layer(160) is positioned between the first substrate and the second substrate, and on one side of the second substrate.
Abstract translation: 目的：提供一种用于制造堆叠半导体器件的方法和由其制造的堆叠半导体器件，以通过同时形成接触插塞和外部线来简化工艺步骤。 构成：至少一个第一晶体管被布置在第一衬底（100）上。 第一源极区域和第一漏极区域（106）布置在第一晶体管的两侧。 第一接触插塞（1510）的下侧与第一源极区域和第一漏极区域接触。 第二基板（200）布置在第一基板上。 至少一个第二接触插塞（1520）的上侧连接到外部布线。 第一接触插塞的上侧和第二基板的上侧位于同一平面上。 第一层间绝缘层（160）位于第一基板和第二基板之间，并且位于第二基板的一侧。
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公开(公告)号：KR1020090131948A
公开(公告)日：2009-12-30
申请号：KR1020080057963
申请日：2008-06-19
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/28 , H01L21/8247
CPC classification number: H01L27/11519 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L2924/0002 , H01L21/28273 , H01L27/2463 , H01L2924/00
Abstract: PURPOSE: A semiconductor device, a manufacturing method thereof, and an electric device including the same are provided to minimize a loss of integration of a semiconductor device by preventing extension of a chip size due to use of an additional plug or width extension of a top common source line. CONSTITUTION: First conductive regions are positioned to a bottom semiconductor layer(100). A top semiconductor layer(200) is laminated on the bottom semiconductor layer. Second conductive regions are positioned to the top semiconductor layer. A bottom conductive line is formed under the top semiconductor layer, and is electrically connected to the first conductive regions. A top conductive line is formed on the top semiconductor layer, and is electrically connected to the second conductive regions. A first conductive plug(315D) electrically connects the bottom conductive line to the top conductive line, and passes a through hole of the top semiconductor layer.
Abstract translation: 目的：提供一种半导体器件及其制造方法以及包括该半导体器件的电子器件，以通过防止由于使用附加插头或顶部的宽度延伸而使芯片尺寸的扩展来最小化半导体器件的集成损失 共同源线。 构成：第一导电区域位于底部半导体层（100）。 顶部半导体层（200）层压在底部半导体层上。 第二导电区域位于顶部半导体层。 底部导电线形成在顶部半导体层之下，并且电连接到第一导电区域。 顶部导电线形成在顶部半导体层上，并且电连接到第二导电区域。 第一导电插头（315D）将底部导电线电连接到顶部导电线，并且通过顶部半导体层的通孔。
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公开(公告)号：KR1020090120688A
公开(公告)日：2009-11-25
申请号：KR1020080046619
申请日：2008-05-20
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/2463 , H01L21/76877 , H01L21/76897 , H01L27/2436
Abstract: PURPOSE: A stack-layered nonvolatile memory device, a method of manufacturing the same and a memory card and a system including the same are provided to form the top parts of a common source line and/or a bit line contact plug in a lower portion than the top part of a gate structure, thereby improving device reliability by preventing defects of a contact. CONSTITUTION: A stack-layered nonvolatile memory device includes a lower memory layer, lower contact units, an upper memory layer, and upper contact units. The lower memory layer(1) includes a lower active area and a plurality of lower gate structures. The upper contact units are electrically connected to the active area. Partial top parts of the upper contact units are formed in a lower portion than the top part of the upper gate structures.
Abstract translation: 目的：提供堆叠分层的非易失性存储器件，其制造方法和存储卡以及包括其的系统，以形成下部的公共源线和/或位线接触插塞的顶部 比栅极结构的顶部，从而通过防止接触的缺陷来提高器件的可靠性。 构成：堆叠分层的非易失性存储器件包括下存储层，下接触单元，上存储层和上接触单元。 下部存储层（1）包括下部有源区域和多个下部栅极结构。 上接触单元电连接到有源区。 上接触单元的部分顶部形成在比上栅极结构的顶部更低的部分中。
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公开(公告)号：KR1020090066022A
公开(公告)日：2009-06-23
申请号：KR1020070133606
申请日：2007-12-18
Applicant: 삼성전자주식회사
IPC: H01B1/20
CPC classification number: C09D11/322 , C09D11/52 , H01L51/0022
Abstract: An electrode composition for ink jet printing, and an electrode and a secondary battery using the composition are provided to improve the adhesion of an electrode component and a current collector and to enhance printing efficiency. An electrode composition for ink jet printing comprises an oxide, a conducting agent, a moisturizer, a binder having a viscosity of 1-100 cps in 1 wt% aqueous solution, and an aqueous solvent. The oxide is an electrode active material of a secondary battery.
Abstract translation: 提供一种用于喷墨印刷的电极组合物和使用该组合物的电极和二次电池，以改善电极组件和集电器的粘附性并提高印刷效率。 用于喷墨印刷的电极组合物包括氧化物，导电剂，保湿剂，在1重量％水溶液中粘度为1-100cps的粘合剂和水性溶剂。 氧化物是二次电池的电极活性物质。
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公开(公告)号：KR100853193B1
公开(公告)日：2008-08-21
申请号：KR1020070002110
申请日：2007-01-08
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76237 , H01L21/765 , H01L21/823481 , H01L23/552 , H01L23/585 , H01L24/02 , H01L2223/6688 , H01L2924/12044
Abstract: 반도체 소자 및 그 형성방법이 제공된다. 상기 반도체 소자는 디지털 회로 영역과 아날로그 회로 영역을 포함하는 반도체 기판, 상기 디지털 회로 영역과 상기 아날로그 회로 영역의 경계에 제공되는 소자분리막, 상기 소자분리막의 측면과 바닥면에 인접하는 도전 영역 및 상기 도전 영역과 전기적으로 연결되며 접지 전압이 인가되는 접지 패드를 포함한다.
디지털 회로 영역, 아날로그 회로 영역, 노이즈Abstract translation: 提供了一种半导体器件及其形成方法。 半导体器件隔离膜，所述导电区域和所述导电相邻的侧面和设置在所述半导体基板的所述边界所提供的隔离膜的底表面上，并且所述数字电路区域和包括数字电路区域和模拟电路区域的模拟电路区域， 并且接地垫电连接到地并且接地电压被施加到该接地垫。
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Patent Agency Ranking
公开(公告)号：KR100713514B1
公开(公告)日：2007-05-02
申请号：KR1020010011336
申请日：2001-03-06
Applicant: 삼성전자주식회사
Inventor： 김한수
IPC: H04L12/50
Abstract: 본 발명은 프로세서간 통신(Inter Processor Communication: IPC) 방식을 사용하는 시스템의 프로세서간 통신 장치 및 방법에 관한 것으로, 특히 유토피아 맵퍼(UTOPIA Mapper)를 이용하여 프로세서간 통신을 수행하는 통신장치 및 방법에 관한 것이다. 이러한 본 발명은 프로세서간 통신을 수행하고 물리층 보드인 제1인접보드 정합부를 구비하는 시스템에 있어서, 프로세서간 통신 셀만을 인터페이스하는 복수개의 유토피아 포트들을 구비하고, 상기 제1인접보드 정합부와 셀들의 인터페이스를 수행하는 제2인접보드 정합부와, 소정의 프로세서간 통신 셀 입력 시 상기 프로세서간 통신 셀에 대한 해당 동작을 수행하고 프로세서간 통신 셀 발생 시 상기 프로세서간 통신 셀을 전송할 유토피아 포트에 대한 유토피아 어드레스를 상기 프로세서간 통신 셀에 삽입하여 출력하는 제어부와, 상기 유토피아 포트들에 대한 유토피아 어드레스를 구비하고, 상기 유토피아 포트를 통해 상기 프로세서간 통신 셀이 입력되면 상기 유토피아 포트에 대한 유토피아 어드레스와 함께 상기 프로세서간 통신 셀을 상기 제어부로 출력하고, 상기 제어부로부터 입력되는 프로세서간 통신 셀의 유토피아 어드레스에 해당하는 유토피아 포트를 통해 제어보드로 전송하는 유토피아 맵퍼로 이루어짐을 특징으로 한다.
IPC, UTOPIA Address, UTOPIA Mapper-
公开(公告)号：KR100578137B1
公开(公告)日：2006-05-10
申请号：KR1020040024206
申请日：2004-04-08
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: 저항 소자를 구비하는 반도체 장치 및 그 제조 방법을 제공한다. 이 저항 소자는 반도체기판의 소정영역 상부에 배치된 저항 패턴, 상기 저항 패턴을 포함하는 반도체기판 상에 배치되어 상기 저항 패턴의 양단을 노출시키는 개구부들을 구비하는 층간절연막 및 상기 개구부들을 채우면서 상기 저항 패턴의 양단에 접속하는 플러그 패턴들을 포함한다. 이때, 상기 플러그 패턴은 상기 저항 패턴과 동일한 물질로 형성된다.
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公开(公告)号：KR1020040040683A
公开(公告)日：2004-05-13
申请号：KR1020020068878
申请日：2002-11-07
Applicant: 삼성전자주식회사
IPC: H01L21/027
Abstract: PURPOSE: An exposure progressing method for manufacturing a semiconductor device is provided to be capable of restraining the bridge phenomenon between patterns having a micro interval with each other. CONSTITUTION: More than two multi-step exposure masks are prepared. At least one out of the multi-step exposure masks is formed as a no pattern mask and the others are formed as predetermined pattern masks. Photoresist layers are sequentially coated on a substrate by using the no pattern mask and the predetermined pattern mask. Then, an exposure process is performed on the resultant structure. Preferably, a phase transition mask is used when preparing the multi-step exposure masks. At this time, the phase transition mask has the predetermined transmittance.
Abstract translation: 目的：提供一种用于制造半导体器件的曝光进行方法，以能够抑制具有微小间隔的图案之间的桥接现象。 规定：准备两个以上的多步骤曝光掩模。 多步曝光掩模中的至少一个形成为无图案掩模，并且其它的形成为预定图案掩模。 通过使用无图案掩模和预定图案掩模，将光致抗蚀剂层顺序地涂布在基板上。 然后，对结果进行曝光处理。 优选地，在制备多步曝光掩模时使用相变掩模。 此时，相变掩模具有预定的透射率。
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公开(公告)号：KR1020010028983A
公开(公告)日：2001-04-06
申请号：KR1019990041545
申请日：1999-09-28
Applicant: 삼성전자주식회사
IPC: H04L12/28
CPC classification number: H04L12/5601 , H04L2012/562 , H04L2012/5652 , H04L2012/5682
Abstract: PURPOSE: A device for controlling a non-real time traffic in an ATM(Asynchronous Transfer Mode) device is provided to monitor states of a switch queue to control a switch rate, and to perform an EPD(Early Packet Discard) when a reference value of a UBR(Unspecified Bit Rate) queue exceeds. CONSTITUTION: A receiving subscriber interface(311) stores cells received from a subscriber card and a trunk, and outputs the cells by a FIFO(First-In-First-Out) method. A switch(312) routs the cells according to header information, and outputs the cells to a transmitting subscriber interface. The transmitting subscriber interface stores the cells outputted from the switch(312), and outputs the cells by the FIFO method. An output queue monitor(315) monitors a threshold value of a transmitting FIFO of the transmitting subscriber interface. If a speed difference is over a setup threshold value, the output queue monitor(315) notifies the receiving subscriber interface(311) of that the speed difference is over the setup threshold value, and reduces a transmission data capacity by a receiver(311). If the threshold value of the transmitting FIFO is below the setup threshold value, the output queue monitor(315) transmits a signal for releasing an alarm state to the receiving subscriber interface(311).
Abstract translation: 目的：提供一种用于控制ATM（异步传输模式）设备中的非实时流量的设备，用于监视交换机队列的状态以控制切换速率，并且当参考值（早期分组丢弃）时，执行EPD 的UBR（未指定比特率）队列超过。 构成：接收用户接口（311）存储从用户卡和中继线接收的信元，并通过FIFO（先进先出）方式输出信元。 交换机（312）根据报头信息对该小区进行路由，并将该小区输出到发送用户接口。 发送用户接口存储从开关（312）输出的单元，并通过FIFO方式输出单元。 输出队列监视器（315）监视发送用户界面的发送FIFO的阈值。 如果速度差超过设定阈值，则输出队列监视器（315）向接收用户界面（311）通知速度差超过建立阈值，并且通过接收机（311）降低传输数据容量， 。 如果发送FIFO的阈值低于建立阈值，则输出队列监视器（315）向接收用户接口（311）发送用于释放报警状态的信号。
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公开(公告)号：KR1020010011200A
公开(公告)日：2001-02-15
申请号：KR1019990030447
申请日：1999-07-26
Applicant: 삼성전자주식회사
Inventor： 김한수
IPC: H04Q1/00
Abstract: PURPOSE: A subscriber matching apparatus is provided to increase system efficiency by dispersing and processing load caused to manipulate subscriber link information or state management information. CONSTITUTION: A subscriber matching apparatus comprises ATM layer processing parts(24a,24b) which make an ATM cell become an internal cell with added routing information and transfer the ATM cell to switch link matching parts(26a,26b), in case where the ATM cell is a user cell. The matching parts(26a,26b) converts the internal cell into an ATM cell to transfer the converted cell to physical layer interfaces(22a,22b), which process frame information. The matching parts(26a,26b) converts an internal cell from the processing parts(24a,24b) into a switch internal cell format to transfer the converted result to a switch network through a switch link of a switch module(10). The matching parts(26a,26b) converts a cell received through the switch link into an original format to transfer the converted result to the processing parts(24a,24b).
Abstract translation: 目的：提供一种订户匹配装置，通过分散和处理为操纵订户链接信息或状态管理信息而引起的负担来提高系统效率。 构成：用户匹配装置包括ATM层处理部分（24a，24b），其使得ATM信元变成具有添加的路由信息的内部小区，并且在ATM的情况下传送ATM信元以切换链路匹配部分（26a，26b） 单元格是用户单元格。 匹配部分（26a，26b）将内部小区转换为ATM信元，将转换的小区传送到处理帧信息的物理层接口（22a，22b）。 匹配部分（26a，26b）将内部单元从处理部分（24a，24b）转换成开关内部单元格式，以通过开关模块（10）的开关链路将转换结果传送到开关网络。 匹配部分（26a，26b）将通过开关链路接收的单元转换成原始格式，以将转换的结果传送到处理部分（24a，24b）。
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