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公开(公告)号：KR1020050060301A
公开(公告)日：2005-06-22
申请号：KR1020030091885
申请日：2003-12-16
Applicant: 한국전자통신연구원
IPC: H04L9/06
CPC classification number: H04L9/0625 , H04L9/0637 , H04L2209/125 , H04L2209/24
Abstract: 한국 표준 암호 알고리즘(SEED) 암호화/복호화 장치에 관한 것으로서 특히, 파이프라인 기법과 병렬 프로세싱 기법을 사용하여 고속 처리를 가능하게 한 SEED 암/복호화 장치, 암/복호화 방법, 라운드 처리 방법, 이에 적합한 F함수 처리기, 그리고 보안 시스템에 관한 것이다.
본 발명에 따른 SEED 암/복호화 장치는 외부 프로세서와의 인터페이스를 위한 인터페이스 처리부; 암/복호 데이터 저장을 위한 데이터 메모리; SEED 암호 알고리즘을 연산하기 위한 제1 및 제2의 SEED 코어들; 상기 제1 및 제2 SEED 코어들에서 필요한 라운드별 키 값들을 생성하는 키 스케줄러; 및 SEED 암/복호 동작에 필요한 동작 모드, 초기값 등을 저장하며, 상기 제1 및 제2 SEED 코어들과 데이터 메모리, 키 스케줄러를 제어하기 위한 SEED 제어기를 포함하는 것을 특징으로 한다.
SEED 암/복호화 장치는 SEED 암호 연산을 지원하지 않는 상용 보안 프로세서들과 PCI 인터페이스를 통하여 연동하게 함으로써 전체 보안 시스템의 처리 성능을 향상시킬 수 있다는 효과를 가진다.-
公开(公告)号：KR100480996B1
公开(公告)日：2005-04-07
申请号：KR1020020082202
申请日：2002-12-21
Applicant: 한국전자통신연구원
IPC: G06F7/00
Abstract: 본 발명은 유한체 GF(2
m )에서 하드웨어 구현에 효율적인 역수 연산 장치 및 방법에 관한 것으로, GF(2
m )의 두 원소 a(x)와 f(x)에서, 모듈러 f(x)에 대한 a(x)의 역수 a
-1 (x)를 계산한다. 이를 위해 본 발명의 역수 연산 장치에서는 u=a(x), v=f(x), c=0, b=1을 설정하고, u=1이 될 때까지 반복하는 연산에서 u의 하위값과 b의 하위값을 2 비트 이상 동시에 처리하는 단계와, u와 v, c, b를 동시에 병렬로 처리하는 단계와, u와 v의 차수를 비교하는 처리와 u의 하위값 처리가 동시에 이루어지는 단계가 첨가되도록 수정된 MAIA 알고리즘을 구현하며, 이러한 알고리즘의 하드웨어 구현을 위하여 역수 연산의 입력값 및 중간 연산 결과를 저장하기 위한 4개의 u, v, c, b 연산 레지스터와, u, v 연산 레지스터의 입력값 연산 및 선택을 위한 2개의 u, v 입력처리기와, 차수를 검색하기 위한 차수 검색기와, 차수 비교 및 새로운 차수 생성을 위한 차수 비교 생성기와, u, v의 차수 값을 저장하기 위한 du, dv 차수 레지스터와, du 차수 레지스터의 입력값 선택을 위한 du 입력 처리기, 그리고 이들 모든 블록들을 제어하기 위한 제어기를 포함하는 역수 연산 장치를 구현한다. 본 발명은 이와 같이 기존의 MAIA를 변형하여 이를 하드웨어로 구현하였으며, 이를 통하여 많은 시간이 소요되는 유한체 GF(2
m )에서의 역수 연산을 효율적으로 빠르게 수행할 수 있도록 하는 이점이 있다.-
公开(公告)号：KR100449491B1
公开(公告)日：2004-09-21
申请号：KR1020010078127
申请日：2001-12-11
Applicant: 한국전자통신연구원
IPC: G06F7/44
Abstract: PURPOSE: A device for a modular multiplication is provided to execute a modular multiplication at high speed by repeating a bit multiplication and executing a modular multiplication of data more than a specific bit, thereby reducing a circuit area of a modular multiplication device, and a reducing memory accessing times using a register for storing a mid-point. CONSTITUTION: A memory(160) stores data for executing a modular multiplication of information. A processor requests the modular multiplication and loads/uses the multiplication results from the memory(160). A register(230) receives data for a modular multiplication from the memory(160), stores the data, and stores a mid-point being generated during the modular multiplication. A modular circuit(240) repeats a bit multiplication calculation, executes a modular multiplication of data which are greater than a specific bit, and stores a mid-point in the register(230) and a result value in the memory(160). A reduction circuit(250) corrects the result value selectively in accordance with a comparison result of the result value and the modular value. A control circuit(220) outputs various kinds of control signals to the register(230), the modular circuit(240), and the reduction circuit(250), and controls the modular multiplication.
Abstract translation: 目的：提供一种用于模乘的设备，用于通过重复比特乘法并且执行比特定比特更多的数据的模乘，从而减少模乘设备的电路面积，并且减少 存储器访问时间使用寄存器来存储中间点。 构成：存储器（160）存储用于执行信息的模乘的数据。 处理器请求模乘法并加载/使用来自存储器（160）的乘法结果。 寄存器（230）从存储器（160）接收用于模乘的数据，存储数据，并且存储在模乘运算期间产生的中点。 模块电路（240）重复比特乘法计算，执行大于特定比特的数据的模乘，并且将中点存储在寄存器（230）中并将结果值存储在存储器（160）中。 减法电路（250）根据结果值和模值的比较结果选择性地校正结果值。 控制电路（220）将各种控制信号输出到寄存器（230），模块电路（240）和缩小电路（250），并控制模乘。
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公开(公告)号：KR1020040055509A
公开(公告)日：2004-06-26
申请号：KR1020020082202
申请日：2002-12-21
Applicant: 한국전자통신연구원
IPC: G06F7/00
Abstract: PURPOSE: A device and a method for a reciprocal operation on the finite field GF are provided to facilitate the realization/expansion of a reciprocal operation device and realize a fast process of an elliptical curve encryption device by performing the reciprocal operation as calculating a reciprocal number of a modular for two elements of the GF(2¬m). CONSTITUTION: The storages(400-700) store an initial input value and a halfway operation result of the reciprocal operation. Input processors(100,200) perform/select the operation for the input value stored in the storages. A degree searcher(800) searches a degree of an operation result value. A degree comparison generator(900) compares the searched degrees and generates a new degree. A controller(300) controls respective tools for the reciprocal operation.
Abstract translation: 目的：提供一种用于在有限域GF上进行互逆运算的装置和方法，以便于实现/扩展相互运算装置，并通过执行往复运算来实现椭圆曲线加密装置的快速处理，从而计算相互数 的模块化用于GF（2m）的两个元件。 规定：存储（400-700）存储初始输入值和相互操作的中途运算结果。 输入处理器（100,200）执行/选择存储在存储器中的输入值的操作。 度数搜索器（800）搜索运算结果值的程度。 度数比较发生器（900）比较搜索度并产生新的度数。 控制器（300）控制用于相互操作的相应工具。
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Patent Agency Ranking
公开(公告)号：KR100436814B1
公开(公告)日：2004-06-23
申请号：KR1020010081717
申请日：2001-12-20
Applicant: 한국전자통신연구원
IPC: G06F7/552
Abstract: Disclosed is an RSA cryptographic processing apparatus capable of performing the fast operating function. A modular multiplication operation or a modular exponentiation operation, i.e., an RSA cryptographic operation, is selectively performed according to a control signal inputted, the modular operation of the data of 512 to 1024 bits is iteratively performed by use of 32-bit operating unit, and the data of 512 to 1024 bits is operated by use of a 32-bit operating unit, thereby minimizing the size of the register storing the data and reducing the size of the cryptographic apparatus, and which the intermediate value generated at the operation process is stored in the internal register instead of the memory, thereby minimizing the times of access to the memory.
Abstract translation: 公开了一种能够执行快速操作功能的RSA密码处理装置。 根据输入的控制信号选择性地执行模乘运算或模幂运算（即RSA密码运算），通过使用32位操作单元迭代地执行512至1024位数据的模运算， 并且通过使用32位操作单元来操作512到1024位的数据，由此使存储数据的寄存器的大小最小化并且减小密码设备的尺寸，并且在操作过程中生成的中间值是 存储在内部寄存器而不是存储器中，从而最大限度地减少对存储器的访问次数。
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公开(公告)号：KR100406137B1
公开(公告)日：2003-11-14
申请号：KR1020010074630
申请日：2001-11-28
Applicant: 한국전자통신연구원
IPC: H04L9/14
Abstract: PURPOSE: A high-speed hardware cryptographic processing system and a method thereof are provided to enhance the performance of a cryptographic process by performing a symmetric key and an asymmetric key ciphering algorithm in parallel. CONSTITUTION: A scheduler(120) is used for generating the scheduling information for an executing procedure of a ciphering algorithm. A storage portion(130) stores rearranged command, rearrangement information, and the address information of the cryptographic data according to the scheduling information. A cryptographic processing portion(150) reads the stored data of the storage portion and performs a cryptographic process according to the command priority by referring to the command rearrangement information and the address information. A control portion(140) outputs a command to generate the scheduling information, sort cryptographic data, assign the data, and perform the cryptographic process.
Abstract translation: 目的：提供一种高速硬件密码处理系统及其方法，通过并行执行对称密钥和非对称密钥加密算法来增强密码处理的性能。 构成：调度器（120）用于生成加密算法的执行过程的调度信息。 存储部分（130）根据调度信息存储重排的命令，重排信息和密码数据的地址信息。 密码处理部分（150）读取存储部分的存储数据，并通过参考命令重排信息和地址信息根据命令优先级执行密码处理。 控制部分（140）输出生成调度信息的命令，对密码数据进行排序，分配数据，并执行密码处理。
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公开(公告)号：KR1020030048632A
公开(公告)日：2003-06-25
申请号：KR1020010078588
申请日：2001-12-12
Applicant: 한국전자통신연구원
IPC: G09C1/00
CPC classification number: H04L9/0625 , H04L2209/125 , H04L2209/24
Abstract: PURPOSE: An encryption device using a Kasumi encryption algorithm is provided to reduce the power consumption by forming around circuit with an FO block and an F1 block. CONSTITUTION: A register portion(100) stores selectively one of plaintext data and input data. A secret key scheduler(150) generates a secret key to encrypt the plaintext data. An FL block(160) is used for calculating output data of the register portion and the secret key by using an FL function of a Kasumi encryption algorithm. An FO block(170) the output data of the register portion and the secret key by using an F1 function of the Kasumi encryption algorithm. An adder portion(180A) performs an exclusive logical OR operation for each output data of the FO block and the F1 block and the output data of the register portion. An input/output control portion(200A) selects the input data of the FO block and the F1 block and a path of the output data.
Abstract translation: 目的：提供使用Kasumi加密算法的加密设备，以通过与FO块和F1块形成围绕电路来降低功耗。 构成：寄存器部分（100）选择性地存储明文数据和输入数据之一。 秘密密钥调度器（150）生成秘密密钥来加密明文数据。 FL块（160）用于通过使用Kasumi加密算法的FL函数来计算寄存器部分和秘密密钥的输出数据。 通过使用Kasumi加密算法的F1函数，FO块（170）寄存器部分的输出数据和秘密密钥。 加法器部分（180A）对FO块和F1块的每个输出数据以及寄存器部分的输出数据执行异或逻辑或运算。 输入/输出控制部分（200A）选择FO块和F1块的输入数据以及输出数据的路径。
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公开(公告)号：KR1020030048631A
公开(公告)日：2003-06-25
申请号：KR1020010078587
申请日：2001-12-12
Applicant: 한국전자통신연구원
IPC: G09C1/00
Abstract: PURPOSE: An apparatus for encoding an elliptic curve is provided to enhance the security and the performance of electronic commercial transaction, electronic cash, identification and key management of an user, and an approval process system by using various elliptic curve protocols. CONSTITUTION: An elliptic curve encoding apparatus includes a register file portion(200), an elliptic curve processor calculation portion(400), an order comparator portion(500), an NAF(Non Adjacent Format) converter portion(100), and an elliptic curve processor control portion(300). The register file portion stores input data and output data to encode an elliptic curve. The elliptic curve processor calculation portion performs a calculation operation for the elliptic curve by using the stored data of the register file portion. The order comparator portion searches and compares the orders necessary for the calculation operation. The NAF converter portion supports the scalar multiplication calculation. The elliptic curve processor control portion generates a control signal to control a calculation operation mode of the elliptic curve processor.
Abstract translation: 目的：提供一种用于编码椭圆曲线的装置，以通过使用各种椭圆曲线协议来增强电子商务交易的安全性和性能，电子现金，用户的识别和密钥管理以及批准过程系统。 构成：椭圆曲线编码装置包括寄存器文件部分（200），椭圆曲线处理器计算部分（400），顺序比较器部分（500），NAF（非相邻格式）转换器部分（100）和椭圆曲线 曲线处理器控制部分（300）。 寄存器文件部分存储输入数据和输出数据以编码椭圆曲线。 椭圆曲线处理器计算部分通过使用寄存器文件部分的存储数据来执行椭圆曲线的计算操作。 订单比较器部分搜索并比较计算操作所需的订单。 NAF转换器部分支持标量乘法运算。 椭圆曲线处理器控制部分生成控制信号以控制椭圆曲线处理器的计算操作模式。
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公开(公告)号：KR1020030042968A
公开(公告)日：2003-06-02
申请号：KR1020010073892
申请日：2001-11-26
Applicant: 한국전자통신연구원
IPC: G06K17/00
Abstract: PURPOSE: A boosting system for an IC card system and a control method thereof are provided to boost a voltage to a desired level in a short time by using an internal voltage in a case that a voltage higher than an internal operation voltage is needed when an IC card system is driven. CONSTITUTION: The circuit comprises a charge storage(130), a booster(150), switches(140, 141), and a switching controller(120). The charge storage(130) stores the power supplied by a power supplier. The booster(150) boosts the voltage, stored at the charge storage(130), to a desired level, and supplies the boosted voltage for the internal circuit of the IC card system. The switches(140, 141) store the power at the charge storage(130) or supply the power according to a switching control signal. The switching controller(120) transmits the switching control signal to the switches(140, 141) according to an operation mode of the internal circuit of the IC card system. The switching controller(120) determines whether the IC card system is in a simple operation mode or a high voltage operation mode in order to transmit the switching control signal, and detects the charge stored at the charge storage(130).
Abstract translation: 目的：提供一种用于IC卡系统的升压系统及其控制方法，用于在需要高于内部工作电压的电压的情况下通过使用内部电压在短时间内将电压提升到所需电平， IC卡系统被驱动。 构成：电路包括电荷存储器（130），升压器（150），开关（140,141）和开关控制器（120）。 充电存储器（130）存储由电源供应的电力。 升压器（150）将存储在电荷存储器（130）处的电压升高到期望的电平，并为IC卡系统的内部电路提供升压电压。 开关（140,141）将电力存储在电荷存储器（130）处，或者根据开关控制信号供电。 切换控制器（120）根据IC卡系统的内部电路的操作模式将切换控制信号发送到开关（140,141）。 切换控制器（120）确定IC卡系统是处于简单操作模式还是高电压操作模式，以便发送开关控制信号，并且检测存储在电荷存储器（130）中的电荷。
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