公开(公告)号：KR100453230B1

公开(公告)日：2004-10-15

申请号：KR1020020069061

申请日：2002-11-08

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  최용제 ,  김무섭 ,  류희수

IPC: H04L9/16

CPC classification number: G06F7/725

Abstract: In an apparatus for a hyperelliptic-curve cryptography processing, an input/output control block controls a peripheral component interconnect (PCI) interface block, a direct memory access (DMA) and a data input/output. An input memory block stores an external instruction and input data provided by the PCI interface block. An output memory block stores a final and an intermediate value of a hyperelliptic-curve cryptography operation. A MUX controls a path of input/output data. An operation core block performs a genus one elliptic-curve and a genus two hyperelliptic-curve cryptography algorithm, respectively. A controlling device controls the operation core block.

Abstract translation: 在用于超椭圆曲线密码处理的设备中，输入/输出控制块控制外围组件互连（PCI）接口块，直接存储器访问（DMA）和数据输入/输出。 输入存储器块存储由PCI接口模块提供的外部指令和输入数据。 输出存储器块存储超椭圆曲线密码术操作的最终值和中间值。 MUX控制输入/输出数据的路径。 运算核心块分别执行属于一个椭圆曲线和属于两个超椭圆曲线密码算法。 控制设备控制运行核心块。

公开(公告)号：KR1020040041186A

公开(公告)日：2004-05-17

申请号：KR1020020069061

申请日：2002-11-08

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  최용제 ,  김무섭 ,  류희수

IPC: H04L9/16

CPC classification number: G06F7/725

Abstract: PURPOSE: A hyperelliptic curve encryption processing system is provided to process a hyperelliptic curve encryption algorithm within a short period of time by performing simultaneously a hyperelliptic curve encryption algorithm having a genus parameter of 1 and the hyperelliptic curve encryption algorithm having the genus parameter of 2. CONSTITUTION: A hyperelliptic curve encryption processing system includes an input/output control block(120), an input memory block(140), an output memory block(150), a MUX(160), an encryption core block(180), and a control unit(170). The input/output control block(120) controls an operation of a PCI interface block, a DMA(Direct Memory Access) operation, and a data input/output operation. The input memory block(140) stores external commands and input data from the PCI interface block. The output memory block(150) stores a result value and an intermediate value of a hyperelliptic curve encryption calculation process. The MUX(160) controls an input/output data path of an input memory block and an output memory block. The encryption core block(180) performs a hyperelliptic curve encryption algorithm having a genus parameter of 1 and the hyperelliptic curve encryption algorithm having the genus parameter of 2 according to the external commands and the input data of the MUX. The control unit(170) controls the encryption core block according to a command of the input memory block.

Abstract translation: 目的：提供超椭圆曲线加密处理系统，通过同时执行属性参数为1的超椭圆曲线加密算法和属性参数为2的超椭圆曲线加密算法，在短时间内处理超椭圆曲线加密算法。 构成：超椭圆曲线加密处理系统包括输入/​​输出控制块（120），输入存储块（140），输出存储块（150），MUX（160），加密核心块（180）和 控制单元（170）。 输入/输出控制块（120）控制PCI接口块的操作，DMA（直接存储器访问）操作和数据输入/输出操作。 输入存储器块（140）存储来自PCI接口块的外部命令和输入数据。 输出存储器块（150）存储结果值和超椭圆曲线加密计算处理的中间值。 MUX（160）控制输入存储块和输出存储块的输入/输出数据路径。 加密核心块（180）根据外部命令和MUX的输入数据执行属性参数为1的超椭圆曲线加密算法，具有属性参数为2的超椭圆曲线加密算法。 控制单元（170）根据输入存储块的命令控制加密核心块。

公开(公告)号：KR1020040055550A

公开(公告)日：2004-06-26

申请号：KR1020030013788

申请日：2003-03-05

Applicant: 한국전자통신연구원

Inventor： 홍도원 ,  류희수 ,  신상욱 ,  장구영 ,  정석원 ,  윤중철 ,  최준 ,  임종인

IPC: G06F7/52

Abstract: PURPOSE: A serial-parallel multiplier finding out the multiplication of two elements on a finite field is provided to quickly find out the multiplication of two elements on finite field by performing the modular subtraction for each operation result again after respectively multiplying the divided two multipliers to a multiplicand. CONSTITUTION: A multiplexer(11) alternatively outputs the first and the second multiplier data depending on a selection signal by receiving the multiplier data in parallel. A half multiplier(12) outputs the first operation value by multiplying the first multiplier to the multiplicand data and performing the modular operation, and outputs the second operation value by multiplying the second multiplier to the multiplicand data and performing the modular operation. A storage(13) stores the first operation value at the first cycle and outputs the stored value at the second cycle depending on a clock doubled to the selection signal. A modular subtracter(14) performs the modular subtraction for subtracting the received first operation value from the second operation value.

Abstract translation: 目的：提供一个串行和并行乘法器，找出有限域上的两个元素的乘法，以便通过在将分割的两个乘法器分别乘以后，再次对每个运算结果执行模式减法，快速找出有限域上的两个元素的乘法 被乘数 构成：多路复用器（11）通过并行地接收乘法器数据来交替地输出取决于选择信号的第一和第二乘法器数据。 半乘法器（12）通过将第一乘法器与被乘数数据相乘并执行模数运算来输出第一运算值，并且通过将第二乘法器乘以乘法数据并执行模数运算来输出第二运算值。 存储器（13）在第一周期存储第一操作值，并且根据与选择信号相加的时钟在第二周期输出存储的值。 模块减法器（14）执行模式减法，以从第二操作值减去接收到的第一操作值。

公开(公告)号：KR1020040050742A

公开(公告)日：2004-06-17

申请号：KR1020020077902

申请日：2002-12-09

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  김호원 ,  최용제 ,  류희수 ,  정교일

IPC: H04L9/30

CPC classification number: H04L9/302 ,  H04L9/3066

Abstract: PURPOSE: A public key encryption apparatus based on the prime field is provided, which improves the efficiency of the system as well is commonly utilized in various system required to operate encryption operation. CONSTITUTION: A public key encryption apparatus(100) based on the prime field includes a register(110), an RSA operational block(160), a modular inverse element calculation block(175), an ellipse curve calculation block(180), a modular operational block(170) and a controller(130). The register(110) stores the various data for the encryption operation. The RSA operational block(160) performs the RSA public key encryption operation. The modular inverse element calculation block(175) calculates the inverse element of the data based on the prime field. The ellipse curve calculation block(180) performs the ellipse curve public key encryption operation. The modular operational block(170) performs the repeat operation in the unit of the 32 bits so as to perform the RSA/ellipse curve encryption operations. And, the controller(130) reads/writes the data required to the encryption operation from the register(110) and controls the operations of each block to perform the encryption operation.

Abstract translation: 目的：提供基于素数字段的公钥加密装置，提高了系统的效率，并且通常用于操作加密操作所需的各种系统。 构成：基于主场的公开密钥加密装置（100）包括寄存器（110），RSA操作块（160），模块化反向元素计算块（175），椭圆曲线计算块（180）， 模块化操作块（170）和控制器（130）。 寄存器（110）存储用于加密操作的各种数据。 RSA操作块（160）执行RSA公钥加密操作。 模块逆元素计算块（175）基于素数域计算数据的逆元素。 椭圆曲线计算块（180）执行椭圆曲线公钥加密操作。 模块化操作块（170）以32位为单位执行重复操作，以便执行RSA /椭圆曲线加密操作。 并且，控制器（130）从寄存器（110）读取/写入加密操作所需的数据，并控制每个块的操作以执行加密操作。

公开(公告)号：KR100416233B1

公开(公告)日：2004-01-31

申请号：KR1020010082619

申请日：2001-12-21

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  박영수 ,  류희수

IPC: H04L9/14

Abstract: PURPOSE: An encryption system for an F8 encryption algorithm and an F9 integrity verification algorithm of IMT(International Mobile Telecommunication)-2000 system is provided to enhance the security of data by using a data encryption calculator between a terminal and an RNC system. CONSTITUTION: An encryption system includes an input/output system bus(10), a register file(11), a memory portion(13), and an F8_F9 calculator(12). The register file is used for storing input variables of an F8 encryption algorithm and an F9 integrity verification algorithm. The memory portion stores encoded output data and authentication code generation object data of the F8 encryption algorithm and the F9 integrity verification algorithm. The F8_F9 calculator performs selectively the F8 encryption algorithm and the F9 integrity verification algorithm in order to provide a message authentication code to the register file and output the encoded output data to the memory portion.

Abstract translation: 目的：提供IMT（国际移动电信）-2000系统的F8加密算法和F9完整性验证算法的加密系统，以通过在终端和RNC系统之间使用数据加密计算器来增强数据的安全性。 组成：加密系统包括输入/​​输出系统总线（10），寄存器文件（11），存储器部分（13）和F8_F9计算器（12）。 寄存器文件用于存储F8加密算法和F9完整性验证算法的输入变量。 存储器部分存储F8加密算法和F9完整性验证算法的编码输出数据和认证码生成对象数据。 F8_F9计算器选择性地执行F8加密算法和F9完整性验证算法，以便向寄存器文件提供消息认证码并将编码的输出数据输出到存储器部分。

公开(公告)号：KR1020030055732A

公开(公告)日：2003-07-04

申请号：KR1020010085801

申请日：2001-12-27

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  최용제 ,  김무섭 ,  류희수

IPC: H04L9/14

CPC classification number: H04L9/14 ,  H04L2209/125

Abstract: PURPOSE: An encryption processing apparatus for a high speed radio network switch is provided to process much data at a time with high throughput and little response time and to process little data rapidly with a little delay time. CONSTITUTION: According to the encryption processing apparatus for a high speed radio network switch performing security processing and integrity verification encryption algorithm processing in the high speed radio network switch, a memory memorizing device part(101) stores input/output protocol packet or data and command and control signals extracted from the packet. A shared memory memorizing device part(102) stores a packet and a control signal and command and data extracted from the packet. A memory control part(105) performs input/output control and synchronization of the memory memorizing device part and the shared memory memorizing device part. An encryption processing device part(107) processes security and integrity verification encryption algorithm. An external input/output control part(108) controls external input/output. An external network interface block(109) performs packet analysis operation as to a packet received from an external network connection network, and transmits the analyzed packet to the encryption processing device part or the memory memorizing device part or the shared memory memorizing device part. And a central processing part(100) performs basic protocol analysis and packet processing, memory management, shared memory management and encryption processor control.

Abstract translation: 目的：提供一种用于高速无线网络交换机的加密处理装置，以高吞吐量和较小的响应时间一次处理大量数据，并在稍微延迟的时间内快速处理一些数据。 构成：根据在高速无线网络交换机中执行安全处理和完整性验证加密算法处理的高速无线网络交换机的加密处理装置，存储器存储装置部分（101）存储输入/输出协议分组或数据和命令 以及从分组提取的控制信号。 共享存储器存储设备部分（102）存储从分组提取的分组和控制信号以及命令和数据。 存储器控制部分（105）执行存储器存储器件部分和共享存储器存储器件部分的输入/输出控制和同步。 加密处理设备部分（107）处理安全性和完整性验证加密算法。 外部输入/输出控制部分（108）控制外部输入/输出。 外部网络接口块（109）对从外部网络连接网络接收到的分组执行分组分析操作，并将分析的分组发送到加密处理装置部分或存储器存储装置部分或共享存储器存储装置部分。 并且中央处理部分（100）执行基本协议分析和分组处理，存储器管理，共享存储器管理和加密处理器控制。

公开(公告)号：KR1020030052602A

公开(公告)日：2003-06-27

申请号：KR1020010082619

申请日：2001-12-21

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  박영수 ,  류희수

IPC: H04L9/14

CPC classification number: H04L9/0625

Abstract: PURPOSE: An encryption system for an F8 encryption algorithm and an F9 integrity verification algorithm of IMT(International Mobile Telecommunication)-2000 system is provided to enhance the security of data by using a data encryption calculator between a terminal and an RNC system. CONSTITUTION: An encryption system includes an input/output system bus(10), a register file(11), a memory portion(13), and an F8_F9 calculator(12). The register file is used for storing input variables of an F8 encryption algorithm and an F9 integrity verification algorithm. The memory portion stores encoded output data and authentication code generation object data of the F8 encryption algorithm and the F9 integrity verification algorithm. The F8_F9 calculator performs selectively the F8 encryption algorithm and the F9 integrity verification algorithm in order to provide a message authentication code to the register file and output the encoded output data to the memory portion.

Abstract translation: 目的：提供IMT（国际移动通信）-2000系统的F8加密算法和F9完整性验证算法的加密系统，通过使用终端与RNC系统之间的数据加密计算器来增强数据的安全性。 构成：加密系统包括输入/​​输出系统总线（10），寄存器文件（11），存储器部分（13）和F8_F9计算器（12）。 寄存器文件用于存储F8加密算法和F9完整性验证算法的输入变量。 存储器部分存储F8加密算法和F9完整性验证算法的编码输出数据和认证码生成对象数据。 F8_F9计算器选择性地执行F8加密算法和F9完整性验证算法，以便向寄存器文件提供消息验证码并将编码的输出数据输出到存储器部分。

公开(公告)号：KR100388059B1

公开(公告)日：2003-06-18

申请号：KR1020000080993

申请日：2000-12-23

Applicant: 한국전자통신연구원

Inventor： 신상욱 ,  이옥연 ,  류희수 ,  이경현

IPC: H04L9/18

Abstract: PURPOSE: A data encryption system using an asymmetric encryption algorithm and a method thereof are provided, which provides a data secret and a data robustness by encrypting a large quantity of messages in a high speed without additional shared encryption key exchange step. CONSTITUTION: According to the data encryption system, an AONT(All-Or-Nothing) conversion part(105) converts input data into a pseudo message using an All-or-nothing method based on a hash function(103). An OAE(Optimal Asymmetric Encryption) part(111) encrypts a part of the pseudo message converted by the above AONT conversion part using the hash function and an asymmetric encryption algorithm. The above AONT conversion part includes a unit calculating an intermediate byproduct K using a divided input message X and N of n-bit nonce(Random Number) after dividing the input message X, and a unit calculating the pseudo message from the above K.

Abstract translation: 目的：提供了一种使用非对称加密算法的数据加密系统及其方法，该系统通过高速加密大量消息而无需额外的共享加密密钥交换步骤来提供数据秘密和数据鲁棒性。 组成：根据数据加密系统，AONT（全或无）转换部分（105）使用基于散列函数的全有或全无方法将输入数据转换为伪消息（103）。 OAE（最佳非对称加密）部分（111）使用散列函数和非对称加密算法对由上述AONT转换部分转换的伪消息的一部分进行加密。 上述AONT转换部分包括一个单元，该单元使用划分输入消息X之后的n比特乱数（随机数）的分割输入消息X和N来计算中间副产品K，以及从上述K计算伪消息的单元。

公开(公告)号：KR100502071B1

公开(公告)日：2005-07-25

申请号：KR1020020080285

申请日：2002-12-16

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  류희수

IPC: H04L9/00

CPC classification number: H04L9/3066

Abstract: 본 발명은 고성능 타원곡선 암호화 장치 구현에 관한 것으로, 본 발명의 타원곡선 암호화 장치는 타원곡선의 스칼라 곱셈 연산인 kP 연산을 수행한다. 이때, k는 곱셈 상수 값으로 타원곡선 차수(order)보다 작은 임의의 정수값이며, P는 타원곡선 위의 임의의 점, 또는 타원곡선 기저점이다. 즉, 본 발명은 고성능 타원곡선 암호화 장치에 있어 프로젝티브 좌표계에서의 타원곡선 연산 기법과 윈도우 연산 기법을 최적화하며, 또한 기저점의 스칼라 곱셈 연산과 임의의 좌표의 스칼라 곱셈 연산이 모두 효율적으로 수행될 수 있도록 하여 타원곡선 암호 처리의 주된 연산인 스칼라 곱셈 연산을 고속으로 처리 가능하도록 함으로써, 타원곡선 스칼라 곱셈 연산에 대하여 빠른 처리 능력을 보장하며, 이를 통하여 타원곡선 암호 프로토콜이 사용되는 서버 시스템에서 보조 연산 장치로 사용하여 전체 시스템 처리 성능을 향상시킬 수 있는 이점이 있다. 또한 타원곡선 암호화 장치에서 하드웨어 자원을 효율적으로 사용할 수 있게 되어 높은 성능을 얻을 수 있으며, 여러 타원곡선 암호 시스템으로 확장이 용이하게 되는 이점이 있다.

公开(公告)号：KR100498754B1

公开(公告)日：2005-07-01

申请号：KR1020020077902

申请日：2002-12-09

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  김호원 ,  최용제 ,  류희수 ,  정교일

IPC: H04L9/30

Abstract: 본 발명은 시스템의 보안성과 기밀성을 제공하기 위한 공개키 암호장치에 관한 것이다. 즉 본 발명은 소수체 연산을 기본으로 하는 RSA 암호 알고리즘과 소수체 타원곡선 암호알고리즘을 선택적으로 구동하도록 구현함에 있어, 핵심적인 연산을 수행하는 모듈러 연산장치 및 그 방법과 상기 모듈러 연산장치를 이용하여 RSA 공개키 암호알고리즘과 소수체 타원곡선 공개키 암호알고리즘을 모두 구동 가능하게 구현함으로서, 시스템의 안정성을 증가시키고, 보다 범용적인 활용을 가능하게 하는 이점이 있다.