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公开(公告)号：KR1020050017373A
公开(公告)日：2005-02-22
申请号：KR1020030056071
申请日：2003-08-13
Applicant: 한국전자통신연구원
IPC: H04L12/28
CPC classification number: H04Q11/0067 , H04J14/0226 , H04J14/0227 , H04J14/0232 , H04J14/0247 , H04J14/0252 , H04J14/0282 , H04L12/2801 , H04L47/2441 , H04L69/22 , H04L2012/561 , H04L2012/5658 , H04L2012/5664 , H04N21/2381 , H04N21/4381 , H04N21/643 , H04Q11/0066 , H04Q11/0071
Abstract: PURPOSE: An Ethernet-based broadcasting and communication integrating system and a method thereof are provided to receive a one-way multi-channel CATV broadcasting service and a data communication service through a single line without using another broadcasting line, thereby providing an integrated broadcasting/communication service. CONSTITUTION: A broadcasting program provider(901) manufactures a broadcasting signal. An SO(System Operator)(902) transmits the broadcasting signal to a subscriber. The subscriber's receiving device receives the broadcasting signal. An Ethernet transmission network(903) located between the broadcasting program provider(901) and the SO(902) consists of edge switches(303,304) and a backbone switch. The broadcasting program provider(901) includes a transmission function block which configures an Ethernet broadcasting frame and transmits the frame to the SO(902). The SO(902) includes a distributive center which selects channel broadcasting signals and multiplexes the signals with Internet traffic.
Abstract translation: 目的：提供一种基于以太网的广播和通信集成系统及其方法，用于通过单线接收单向多信道有线电视广播业务和数据通信业务，而不使用另一广播线路，从而提供综合广播/ 通讯服务。 规定：广播节目提供商（901）制作广播信号。 SO（系统操作员）（902）向用户发送广播信号。 订户的接收设备接收广播信号。 位于广播节目提供商（901）和SO（902）之间的以太网传输网络（903）由边缘交换机（303,304）和主干交换机组成。 广播节目提供商（901）包括配置以太网广播帧并将帧发送到SO（902）的传输功能块。 SO（902）包括分配中心，其选择信道广播信号并将信号与互联网业务复用。
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92.发明授权패킷 처리 엔진과 메인 프로세서간에 고속 블록 데이터전송을 수행하는 네트워크 시스템 및 그것의 ＤＭＡ운영방법 失效패킷처리엔진과메메터터터을DMA DMA DMA DMA DMA DMA DMA운법
公开(公告)号：KR100441884B1
公开(公告)日：2004-07-27
申请号：KR1020020020904
申请日：2002-04-17
Applicant: 한국전자통신연구원
IPC: H04L12/771 , G06F13/28
Abstract: PURPOSE: A network system for performing a high-speed block data transmission between a packet processing engine and a main processor, and a method for operating a DMA(Direct Memory Access) thereof are provided to reduce a DMA management function of the main processor and a processing time according to data transmission by setting a control state of a DMA engine in the DMA engine. CONSTITUTION: A processor processing buffer(220) stores packets to be processed in a CPU(110). A packet processing engine(240) forwards a packet inputted from a link in a wired speed, and generates a DMA request signal when the inputted packet is the packet to be processed in the CPU(110). A DMA engine(250) answers to the DMA request signal, monitors a residual quantity state of the processor processing buffer(220), and generates a control signal and an address necessary for a DMA operation.
Abstract translation: 目的：提供一种用于在分组处理引擎和主处理器之间执行高速块数据传输的网络系统，以及一种用于操作DMA（直接存储器访问）的方法，以减少主处理器的DMA管理功能，以及 通过在DMA引擎中设置DMA引擎的控制状态来根据数据传输的处理时间。 构成：处理器处理缓冲器（220）将待处理的分组存储在CPU（110）中。 分组处理引擎（240）以有线速度转发从链路输入的分组，并且当输入分组是要在CPU（110）中处理的分组时，产生DMA请求信号。 DMA引擎（250）回答DMA请求信号，监视处理器处理缓冲器（220）的剩余量状态，并产生DMA操作所需的控制信号和地址。
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公开(公告)号：KR100440576B1
公开(公告)日：2004-07-21
申请号：KR1020010086483
申请日：2001-12-28
Applicant: 한국전자통신연구원
IPC: H04L12/26
Abstract: PURPOSE: A network processor having a packet generator for a test inside and a method for testing a packet path using the same are provided to generates packets for the test without complex software procedures, thereby executing a path test of the packets with only network processor. CONSTITUTION: A packet generator(407) for a test is installed between a physical layer interface(401) and a switch interface(403). The packet generator(407) generates packets for a test under the control of a processor for packet processing, so that the packet generator(407) provides the generated packets to the physical layer interface(401) or the switch interface(403). The packet generator(407) generates the packets appropriate for the physical layer interface(401) or the switch interface(403) according to kinds of interfaces to be tested. The processor for packet processing sets up a loop back path for executing the test.
Abstract translation: 目的：提供一种具有用于内部测试的分组发生器的网络处理器和使用该网络处理器测试分组路径的方法，以在没有复杂的软件过程的情况下产生用于测试的分组，从而仅用网络处理器执行分组的路径测试。 构成：用于测试的分组发生器（407）安装在物理层接口（401）和交换机接口（403）之间。 分组生成器（407）在用于分组处理的处理器的控制下生成用于测试的分组，以便分组生成器（407）将生成的分组提供给物理层接口（401）或交换接口（403）。 分组生成器（407）根据要测试的接口的种类生成适合于物理层接口（401）或交换接口（403）的分组。 用于分组处理的处理器为执行测试设置回路路径。
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公开(公告)号：KR100421414B1
公开(公告)日：2004-03-09
申请号：KR1020010044274
申请日：2001-07-23
Applicant: 한국전자통신연구원
IPC: H04L12/44
Abstract: PURPOSE: A method for retrieving and updating a tree using a node structure of a multi search tree is provided to reduce a retrieving time by increasing the number of keys capable of being stored in a node using one pointer necessary for one node of a B tree and decreasing the level number of tree path. CONSTITUTION: An initial 16-bit array is retrieved using an upper 16-bit segment of an inputted destination IP(Internet Protocol) address(101). It is judged whether an "I" flag of a corresponding entry is true in the retrieved initial 16-bit array(102). If the "I" flag of the corresponding entry is true, it is moved to a root node indicated by a node pointer and a multi-path retrieval is performed using a lower 16-bit offset of the inputted destination IP address(103). It is judged whether an exact matching is achieved before a leaf node is reached(104). If the exact matching is achieved before the leaf node is reached, it is judged whether the arrival of the retrieval is a branch node or a leaf node(105). If the arrival of the retrieval is the leaf node, a region port stored in a register is returned(106).
Abstract translation: 目的：提供一种使用多搜索树的节点结构来检索和更新树的方法，以通过使用B树的一个节点所必需的一个指针增加能够存储在节点中的密钥的数量来减少检索时间 并减少树路径的级数。 构成：使用输入目的IP（互联网协议）地址（101）的高16位段来检索初始的16位数组。 判断是否有“I” 检索到的初始16位数组（102）中的对应条目的标志为真。 如果“I” 标志移动到由节点指针指示的根节点，并且使用输入的目的地IP地址（103）的较低的16位偏移来执行多路径检索。 在达到叶节点之前判断是否达到精确匹配（104）。 如果在到达叶节点之前完成精确匹配，则判断检索的到达是分支节点还是叶节点（105）。 如果检索的到达是叶节点，则返回存储在寄存器中的区域端口（106）。
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公开(公告)号：KR100415585B1
公开(公告)日：2004-01-24
申请号：KR1020010086499
申请日：2001-12-28
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: PURPOSE: An ATM(Asynchronous Transfer Mode) interface device for a high-speed router system is provided to perform an interface with an ATM network which supports a transmission speed with 622Mbps, in an IP(Internet Protocol)-based high-speed router. CONSTITUTION: A physical layer interface unit(201) connects to an ATM network by an optical interface. Transmission/reception cell converting units(209,207) convert an ATM cell into an IP packet type, and convert data inputted as an IP packet type into an ATM cell type. Transmission/reception memories(208,202) store data in the cell conversion of the transmission/reception cell converting units(209,207). A network processor(204) analyzes and processes packet information, forwards processed packet information to an output port, and performs an interface with a switch. A memory(205) stores data when performing the packet processing and forwarding functions. Transmission/reception data bus converting units(213,203) convert a protocol between the network processor(204) and the transmission/reception cell converting units(209,207). A control bus converting unit(212) converts a serial bus into a parallel bus, between the network processor(204) and the physical layer interface unit(201). A host processor(206) manages resources of the entire line interface module of a high-speed router system.
Abstract translation: 目的：提供一种用于高速路由器系统的ATM（异步传输模式）接口设备，用于在基于IP（互联网协议）的高速路由器中与支持622Mbps传输速度的ATM网络进行接口连接。 构成：物理层接口单元（201）通过光接口连接到ATM网络。 发送/接收信元转换单元（209,207）将ATM信元转换成IP分组类型，并将作为IP分组类型输入的数据转换成ATM信元类型。 发送/接收存储器（208,202）将数据存储在发送/接收单元转换单元（209,207）的单元转换中。 网络处理器（204）分析并处理分组信息，将处理后的分组信息转发到输出端口，并执行与交换机的接口。 存储器（205）在执行分组处理和转发功能时存储数据。 发送/接收数据总线转换单元（213,203）转换网络处理器（204）和发送/接收单元转换单元（209,207）之间的协议。 控制总线转换单元（212）在网络处理器（204）和物理层接口单元（201）之间将串行总线转换为并行总线。 主处理器（206）管理高速路由器系统的整个线路接口模块的资源。
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Patent Agency Ranking
公开(公告)号：KR100392383B1
公开(公告)日：2003-07-23
申请号：KR1020000083238
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: G06F12/00
CPC classification number: Y02D10/13
Abstract: 본 발명은 반도체 기술에 관한 것으로, 특히 임베디드 프로세서와 같이 버스 회로를 가진 반도체 칩에 관한 것이며, 칩 면적을 증가시키지 않으면서 버스 회로의 전력소모를 줄일 수 있는 반도체 칩을 제공하는데 그 목적이 있다. 본 발명은 다수의 기능블럭을 구비하는 반도체 칩에 있어서, 하나 이상의 기능블럭이 접속된 제1 버스와, 상기 제1 버스에 접속된 기능블럭을 제외한 하나 이상의 기능블럭이 접속된 제2 버스와, 상기 제1 및 제2 버스를 구동하기 위한 구동 수단을 구비한다.
Abstract translation: 目的：提供具有像嵌入式处理器一样的总线电路的半导体芯片，以在不增加芯片面积的情况下降低总线电路的功耗。 构成：半导体芯片等设备包括总线A（30），总线B（31），CPU（32），注册表文件，DRAM（34），PIO（并行I / O） ，以及驱动器单元（36）。 CPU（32）连接到总线A（30）。 DRAM（34）连接到总线B（31）。 驱动器单元（36）用于驱动总线A（30）和总线B（31）。 即，由半导体芯片构成的多个功能块被分成两组，即连接到总线A（30）的一组频繁访问的功能块和一组相对不频繁的访问功能块，以及 巴士B（31）。 总线驱动器单元包括用于驱动总线B（31）的总线驱动器和用于从总线B（31）接收数据的输入锁存器。 总线驱动器使用三相逆变器，输入锁存器包括一个三相逆变器和两个逆变器。 用于驱动总线A（30）的总线驱动器单元的结构与用于驱动总线B（31）的总线驱动器单元的结构相同。
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公开(公告)号：KR1020020054214A
公开(公告)日：2002-07-06
申请号：KR1020000083238
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: G06F12/00
CPC classification number: Y02D10/13
Abstract: PURPOSE: A semiconductor chip, having a bus circuit like an embedded processor, is provided to reduce power consumption for a bus circuit without increasing an area of a chip. CONSTITUTION: The device, a semiconductor chip, comprises a bus A(30), a bus B(31), a CPU(32), a registry file, a DRAM(34), a PIO(Parallel I/O, 35), and a driver cell(36). The CPU(32) is connected to the bus A(30). The DRAM(34) is connected to the bus B(31). The driver cell(36) is for driving the bus A(30) and the bus B(31). Namely, the plural function blocks, consisting of the semiconductor chip, are partitioned in two groups, i.e. a group of frequently accessing function blocks and a group of relatively infrequently accessing function blocks, which are connected to the bus A(30), and the bus B(31), respectively. The bus driver cell includes a bus driver for driving the bus B(31) and an input latch for receiving data from the bus B(31). The bus driver uses a three phase inverter, and the input latch includes a three phase inverter and two inverters. The structure of the bus driver cell for driving the bus A(30) is the same as that of the bus driver cell for driving the bus B(31).
Abstract translation: 目的：提供具有诸如嵌入式处理器的总线电路的半导体芯片，以减少总线电路的功耗，而不增加芯片的面积。 构成：该器件是半导体芯片，包括总线A（30），总线B（31），CPU（32），注册表文件，DRAM（34），PIO（并行I / O，35） ，以及驱动单元（36）。 CPU（32）连接到总线A（30）。 DRAM（34）连接到总线B（31）。 驱动器单元（36）用于驱动总线A（30）和总线B（31）。 即，由半导体芯片组成的多个功能块被分成两组，即连接到总线A（30）的一组频繁访问功能块和一组相对不常访问的功能块，并且 巴士B（31）。 总线驱动器单元包括用于驱动总线B（31）的总线驱动器和用于从总线B（31）接收数据的输入锁存器。 总线驱动器使用三相逆变器，输入锁存器包括三相逆变器和两个逆变器。 用于驱动总线A（30）的总线驱动器单元的结构与用于驱动总线B（31）的总线驱动器单元的结构相同。
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