-
公开(公告)号：KR100527341B1
公开(公告)日：2005-11-09
申请号：KR1020020080159
申请日：2002-12-16
Applicant: 한국전자통신연구원
IPC: H04L12/00
Abstract: 본 발명은 크로스바 방식의 방송스위치에 관한 것으로서, 입력포트에 매칭되며, 유니캐스트 및 멀티캐스트 데이터를 일시 저장하고, 유니캐스트 및 멀티캐스트 데이터를 목적하는 출력포트 별로 전송하기위한 중재요청을 하고, 중재요청이 수행된 패킷 데이터에 대한 정보를 저장 및 관리하는 적어도 하나의 입력버퍼; 적어도 하나의 입력버퍼로부터 중재요청 신호를 받아 그 요청 정보를 저장 및 관리하며, 중재 요청에 따라 중재를 수행하는 중앙 중재기; 입력버퍼로부터 데이터를 전송받아 중앙 중재기의 중재결과정보를 받아 이에 따라 스위칭을 수행하며, 적어도 둘 이상의 크로스바 스위치를 포함하는 크로스바스위치부; 및 크로스바 스위치부의 크로스바 스위치 각각에 매칭되어 출력된 패킷 데이터를 크로스바 스위치 별로 저장하고 관리하는 출력버퍼들로 이루어진 출력버퍼부를 포함함을 특징으로 한다.
따라서 본 발명에 의하면, 방송 패킷 지원 문제를 해결하고 스위치의 고 처리율을 지원함으로써 방송 서비스에 원활히 대처할 수 있으며 병렬 중재기를 이용하고 파이프라인 방식을 이용한 고속 동작을 지원함으로써 고속의 대용량의 스위치를 적은 비용으로 설계할 수 있다.-
公开(公告)号：KR100520304B1
公开(公告)日：2005-10-13
申请号：KR1020020081381
申请日：2002-12-18
Applicant: 한국전자통신연구원
IPC: H04L1/22
Abstract: 본 발명은 크로스바 스위치의 이중화 장치 및 방법으로서, 그 이중화 장치는 입력버퍼스위치 입력부의 상태정보를 이용하여 중재하고, 자신이 액티브이면 자신의 중재결과를, 스탠바이이면 상대방 액티브 크로스바스위치의 중재결과를 이용하여 입력버퍼스위치 출력부와 포트별로 연결하는 제1크로스바스위치; 및 입력버퍼스위치 입력부의 상태정보를 이용하여 중재하고, 자신이 액티브이면 자신의 중재결과를, 스탠바이이면 상대방 액티브 크로스바스위치의 중재결과를 이용하여 입력버퍼스위치 출력부와 포트별로 연결하는 제2크로스바 스위치를 포함하며, 크로스바 스위치를 플레인 단위의 이중화는 물론 포트 단위의 이중화하여, 어느 한 포트가 고장을 일으킬 때 셀 손실이 최소화 될 수 있다.
-
公开(公告)号：KR1020050038209A
公开(公告)日：2005-04-27
申请号：KR1020030073444
申请日：2003-10-21
Applicant: 한국전자통신연구원
IPC: H03L7/07
Abstract: 본 발명은 클럭 신호의 연속성을 보장하는 클럭 신호 선택 장치 및 방법에 관한 것으로, 적어도 두 개 이상의 클럭 신호들의 위상을 지속적으로 제어하여 클럭 신호들의 위상을 항상 일치시켜준다. 그 결과, 액티브 클럭 신호와 스탠바이 클럭 신호 간에 주파수가 서로 다른 경우에도 절체시 출력 클럭 신호의 연속성이 유지되어, 안정된 클럭 신호를 제공할 수 있게 된다.
-
公开(公告)号：KR1020050025778A
公开(公告)日：2005-03-14
申请号：KR1020030062614
申请日：2003-09-08
Applicant: 한국전자통신연구원
IPC: G06F1/16
Abstract: A device for a mainboard and a sub board to receive a high speed/density interface is provided to separate/fix only the line interface circuit to a line card as a sub board form without designing entire line card again in case that the line interface card embedded in the line card is corrected by change of a network processor or a switch fabric in the line card. A main function circuit(211) performs a main function of the mainboard(210). A combining part(213) is equipped with a sliding part forming a stepped part making the sub board(220) slid/combined by forming a curved face with the mainboard. A connector(212) electrically connects between the mainboard and the sub board.
Abstract translation: 提供用于接收高速/密度接口的主板和子板的装置，以仅将线路接口电路作为子板形式将线路接口电路分离/固定，而不再设计整个线路卡，以防线路接口卡 嵌入在线卡中的线路卡中的网络处理器或交换结构的改变被校正。 主功能电路（211）执行主板（210）的主要功能。 组合部（213）配备有形成台阶部的滑动部，通过与主板形成弯曲面，使副板（220）滑动/组合。 连接器（212）在主板和子板之间电连接。
-
公开(公告)号：KR1020050019266A
公开(公告)日：2005-03-03
申请号：KR1020030056919
申请日：2003-08-18
Applicant: 한국전자통신연구원
CPC classification number: H04L49/60 , H04J3/0691 , H04J3/1611
Abstract: PURPOSE: A TDM/IP data integrated switching system and a method thereof are provided to simultaneously switch all packet-type data using a fixed-length packet switch by converting TDM/EoS(Ethernet over SDH)-mixed data, received from a SONET/SDH network, into the same format as packet data, received from an IP/Ethernet network. CONSTITUTION: A TDM/IP data integrated switching system(200) comprises a TDM/EoS data processor(300), an IP/Ethernet data processor(400), a fixed-length packet switch(500), and a control/timing driver(600). The TDM/EoS data processor(300) comprises an input TDM/EoS data processor(310) and an output TDM/EoS data processor(320). The input TDM/EoS data processor(310) comprises an input data classification part(311), an input EoS data processing part(312), an input TDM data processing part(313), and an input data multiplexer(314). The input data classification part(311) classifies TDM/EoS-mixed data, received from a SONET/SDH network, into TDM data and EoS data. The input EoS data processing part(312) packetizes the classified EoS data through demultiplexing, EoS protocol processing, Ethernet frame processing, and packet header creation. The input TDM data processing part(313) packetizes the classified TDM data through demultiplexing, data alignment, and packet header creation. The input data multiplexer(314) receives packetized data from the input EoS data processing part(312) and multiplexes them.
Abstract translation: 目的：提供一种TDM / IP数据集成交换系统及其方法，通过转换从SONET / EOS接收的TDM / EoS（Ethernet over SDH）混合数据，同时切换所有分组型数据，使用固定长度的分组交换机， SDH网络与从IP /以太网接收的分组数据格式相同。 构成：TDM / IP数据集成交换系统（200）包括TDM / EoS数据处理器（300），IP /以太网数据处理器（400），固定长度分组交换机（500）和控制/定时驱动器 （600）。 TDM / EoS数据处理器（300）包括输入TDM / EoS数据处理器（310）和输出TDM / EoS数据处理器（320）。 输入TDM / EoS数据处理器（310）包括输入数据分类部分（311），输入EoS数据处理部分（312），输入TDM数据处理部分（313）和输入数据多路复用器（314）。 输入数据分类部（311）将从SONET / SDH网络接收的TDM / EoS混合数据分类为TDM数据和EoS数据。 输入EoS数据处理部分（312）通过解复用，EoS协议处理，以太网帧处理和分组报头创建对分类的EoS数据进行打包。 输入TDM数据处理部分（313）通过解复用，数据对准和分组报头创建对分类的TDM数据进行分组。 输入数据多路复用器（314）从输入的EoS数据处理部分（312）接收分组数据，并对其进行复用。
-
Patent Agency Ranking
公开(公告)号：KR1020040054347A
公开(公告)日：2004-06-25
申请号：KR1020020081378
申请日：2002-12-18
Applicant: 한국전자통신연구원
IPC: H04L12/863
CPC classification number: H04L47/6225 , H04L47/6275
Abstract: PURPOSE: A round robin scheduling system having a weight and a method therefor are provided to effectively schedule multiple transmission data flows according to bandwidth weight allocated to each flow. CONSTITUTION: A priority queue(130) manages data in order of being aligned according to tag values. A tag generating/managing unit(110) generates and manages data tags for suitably arranging data of the priority queue(130) to suitably perform scheduling on data. A flow control managing unit(120) excludes corresponding flow control data from scheduling candidates in scheduling when it receives flow control information from a scheduler front end.
Abstract translation: 目的：提供一种具有权重及其方法的循环调度系统，以根据分配给每个流的带宽权重有效地调度多个传输数据流。 构成：优先级队列（130）根据标签值对齐数据。 标签生成/管理单元（110）生成和管理数据标签，用于适当地布置优先级队列（130）的数据以适当地执行对数据的调度。 当从调度器前端接收到流量控制信息时，流量控制管理单元（120）排除相应的流量控制数据，从调度候选中排除。
-
公开(公告)号：KR1020040052306A
公开(公告)日：2004-06-23
申请号：KR1020020080159
申请日：2002-12-16
Applicant: 한국전자통신연구원
IPC: H04L12/00
CPC classification number: H04L49/101
Abstract: PURPOSE: A broadcast switch in crossbar type is provided to finish all operations within a processing time of each unit data packet, and to transmit results of each functional block in pipeline method, thereby increasing a switch throughput. CONSTITUTION: At least one input buffer(200,210) matched with input ports temporarily stores unicast/multicast data, transmits an arbitration request to transmit the data to targeted output ports, and stores/manages information on packet data where the arbitration request is performed. A central arbiter(230) receives an arbitration request signal from the at least one input buffer(200,210) to store/manage requested information, and carries out an arbitration process according to the request. A crossbar switch portion(222) receives the data to switch the data according to arbitration result information, and includes at least more than two crossbar switches. An output buffer portion(224) consists of output buffers that store/manage the packet data by crossbar switch.
Abstract translation: 目的：提供交叉开关类型的广播交换机，以在每个单位数据包的处理时间内完成所有操作，并以流水线方式传输每个功能块的结果，从而增加交换机吞吐量。 构成：与输入端口匹配的至少一个输入缓冲器（200,210）临时存储单播/多播数据，发送仲裁请求以将数据发送到目标输出端口，并存储/管理执行仲裁请求的分组数据的信息。 中央仲裁器（230）从至少一个输入缓冲器（200,210）接收仲裁请求信号以存储/管理所请求的信息，并根据请求执行仲裁处理。 交叉开关部分（222）接收数据以根据仲裁结果信息切换数据，并且包括至少两个以上的交叉开关。 输出缓冲器部分（224）由通过交叉开关存储/管理分组数据的输出缓冲器组成。
-
公开(公告)号：KR100382142B1
公开(公告)日：2003-05-01
申请号：KR1020000027081
申请日：2000-05-19
IPC: H04L12/50
CPC classification number: H04L49/1576 , H04L49/1523 , H04L49/3018 , H04L49/3027 , H04L2012/5679 , H04L2012/5683
Abstract: A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method. The SIM method consists of three operations, those are, request operation, grant operation, and accepting operation, and in the SIM method, the operations are iteratively carried out several times in one cell period, thereby matching efficiency can be increased. Each input buffered module determines simultaneously multiple FIFO queues served in one cell period, so that the SIM method with multiple selection ability has higher speed operations and better performance than conventional scheduling methods.
Abstract translation: 提供了一种用于调度输入和输出缓冲ATM或分组交换的方法，并且更具体地涉及一种用于对适配于高速大开关的输入和输出缓冲开关进行信元调度的方法。 输入和输出缓冲开关具有多个交换平面，其结构用于补偿由输入缓冲交换机的HOL（线头）阻塞导致的输入缓冲交换机的性能下降。 输入和输出缓冲开关由输入缓冲模块组成，多个输入端口和输出端口以及输出缓冲模块组成，每个输入缓冲模块具有用于相关模块输出缓冲模块的多个FIFO队列。 在具有多个交换平面的输入和输出缓冲交换机中，使用简单迭代匹配（SIM）方法执行小区调度。 SIM方法包括三个操作，即请求操作，授权操作和接受操作，并且在SIM方法中，操作在一个单元周期内迭代地执行若干次，由此可以增加匹配效率。 每个输入缓冲模块同时确定在一个小区周期内服务的多个FIFO队列，因此具有多种选择能力的SIM方法比传统调度方法具有更高的速度操作和更好的性能。
-
公开(公告)号：KR1020010064022A
公开(公告)日：2001-07-09
申请号：KR1019990062136
申请日：1999-12-24
IPC: H03L7/06
Abstract: PURPOSE: A differential charge pump circuit having a current leakage blocking function is provided which blocks leakage current path of a loop filter using a self-bias technique to improve the performance of a phase locked loop. CONSTITUTION: A differential charge pump circuit having a current leakage blocking function includes a pair of NMOS switching elements(309,312) for receiving input signals, a pair of PMOS switching elements(305,308) for receiving differential input signals, and a pair of NMOS switching elements(310,311) and PMOS switching elements(306,307) constructing a cross-coupled drain structure. The circuit further has a loop filter(320) for generating an output signal, and current imaging devices (330,340,350,360) for receiving the output signal. The current imaging devices are horizontally symmetrically located in order to control the magnitude of charge and discharge current of the switching elements.
Abstract translation: 目的：提供具有电流泄漏阻断功能的差分电荷泵电路，其利用自偏置技术阻止环路滤波器的漏电流路径，以提高锁相环的性能。 构成：具有漏电阻塞功能的差分电荷泵电路包括用于接收输入信号的一对NMOS开关元件（309,312），用于接收差分输入信号的一对PMOS开关元件（305,308）和一对NMOS开关元件 （310,311）和构成交叉耦合漏极结构的PMOS开关元件（306,307）。 电路还具有用于产生输出信号的环路滤波器（320）和用于接收输出信号的当前成像设备（330,340,350,360）。 当前的成像装置水平对称地定位，以便控制开关元件的充电和放电电流的大小。
-
公开(公告)号：KR1020010063940A
公开(公告)日：2001-07-09
申请号：KR1019990062048
申请日：1999-12-24
IPC: H04L12/28
CPC classification number: H04L49/153 , H04L12/5601 , H04L49/106 , H04L2012/5674
Abstract: PURPOSE: A cell/packet switching system configured with planes is provided to configure multiple planes, to compensate an additional time block for bit and word synchronization for output data of an asynchronous cross pointer/cross bar switch for sequential activation and operation. CONSTITUTION: Input/output buffering units(4100,4200,4300) stores cell/packet inputted at a high speed, for waiting. Cross pointer/cross bar switching units(4410,4420,4430) are configured with multiple planes, for interfacing and switching with the input/output buffering units(4100,4200,4300) through a high speed serial bit stream input/output. A cell/packet arbitrating unit(4500) performs arbitration for the output control of the cell/packet stored in the input/output buffering units(4100,4200,4300), outputs shape change information to the cross pointer/cross bar switching units(4410,4420,4430), and sequentially activates the cross pointer/cross bar switching units(4410,4420,4430) to output the shape change information.
Abstract translation: 目的：提供配置有平面的单元/分组交换系统以配置多个平面，以补偿用于顺序激活和操作的异步交叉指针/交叉开关的输出数据的位和字同步的附加时间块。 规定：输入/输出缓冲单元（4100,4200,4300）存储以高速输入的单元/分组，用于等待。 交叉指针/交叉开关单元（4410,4420,4430）配置有多个平面，用于通过高速串行比特流输入/输出与输入/输出缓冲单元（4100,4200,4300）进行接口和切换。 小区/分组仲裁单元（4500）对存储在输入/输出缓冲单元（4100,4200,4300）中的小区/分组的输出控制执行仲裁，将形状改变信息输出到交叉指针/横杆切换单元 4410,4420,4430），并且顺序地激活交叉指针/横杆切换单元（4410,4420,4430）以输出形状变化信息。
-
-
-
-
-
-
-
-
-
Search Results
362
records
(took 0.033 seconds)
