公开(公告)号：US09540729B1

公开(公告)日：2017-01-10

申请号：US14835456

申请日：2015-08-25

Applicant: ASM IP Holding B.V.

Inventor： Seiji Okura ,  Hidemi Suemori ,  Viljami J. Pore

IPC: C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L49/02 ,  C23C16/40

CPC classification number: C23C16/45529 ,  C23C16/40 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/45531 ,  C23C16/45538 ,  H01L21/02172 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L28/75

Abstract: Processes are provided for depositing titanium nanolaminate thin films that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. In some embodiments a titanium nanolaminate film comprising titanium oxide layers and titanium nitride layers is deposited on a three-dimensional feature, such as an existing mask feature. The conformal titanium nanolaminate film may be directionally etched so that only the titanium nanolaminate deposited or formed on the sidewalls of the existing three-dimensional feature remains. The three-dimensional feature is then removed via an etching process, leaving the pitch doubled titanium nanolaminate film.

Abstract translation: 提供了用于沉积可用于例如集成电路制造中的钛纳米级氨酸盐薄膜的方法，例如在间距倍增过程中形成间隔物。 在一些实施方案中，包含氧化钛层和氮化钛层的钛纳米层合膜被沉积在诸如现有掩模特征的三维特征上。 可以对保形的钛纳米膜进行定向蚀刻，使得仅保留沉积或形成在现有三维特征的侧壁上的钛纳米层状钛。 然后通过蚀刻工艺去除三维特征，留下螺距倍增的钛纳米质膜。

公开(公告)号：US20150299848A1

公开(公告)日：2015-10-22

申请号：US14687833

申请日：2015-04-15

Applicant: ASM IP Holding B.V.

Inventor： Suvi P. Haukka ,  Raija H. Matero ,  Eva Tois ,  Antti Niskanen ,  Marko Tuominen ,  Hannu Huotari ,  Viljami J. Pore

IPC: C23C16/04 ,  C23C16/06 ,  C23C16/56 ,  C23C16/30 ,  C23C16/455 ,  C23C16/02 ,  C23C16/40

CPC classification number: C23C16/04 ,  C23C16/02 ,  C23C16/06 ,  C23C16/18 ,  C23C16/22 ,  C23C16/30 ,  C23C16/402 ,  C23C16/405 ,  C23C16/407 ,  C23C16/408 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/76829 ,  H01L21/76849

Abstract: Methods are provided for dual selective deposition of a first material on a first surface of a substrate and a second material on a second, different surface of the same substrate. The selectively deposited materials may be, for example, metal, metal oxide, or dielectric materials.

Abstract translation: 提供了用于将第一材料双重选择性沉积在基底的第一表面上的方法和在相同基底的第二不同表面上的第二材料。 选择性沉积的材料可以是例如金属，金属氧化物或介电材料。

公开(公告)号：US20150287591A1

公开(公告)日：2015-10-08

申请号：US14686595

申请日：2015-04-14

Applicant: ASM IP HOLDING B.V.

Inventor： Viljami J. Pore ,  Yosuke Kimura ,  Kunitoshi Namba ,  Wataru Adachi ,  Hideaki Fukuda ,  Werner Knaepen ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L21/02

CPC classification number: H01L21/02112 ,  C23C16/045 ,  C23C16/30 ,  C23C16/32 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/2254 ,  H01L21/31111

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C.

Abstract translation: 提供了沉积硼和碳的膜的方法。 在一些实施例中，提供了沉积具有所需性质（诸如保形性和蚀刻速率）的B，C膜的方法。 一种或多种含硼和/或碳的前体可以在低于约400℃的温度下在基材上分解。含硼和碳的一种或多种膜可以具有小于约30埃的厚度。 提供掺杂半导体衬底的方法。 掺杂半导体衬底可以包括通过在大约300℃至大约450℃的工艺温度下将衬底暴露于气相硼前体而在半导体衬底上沉积硼和碳膜，其中硼前体包括硼， 碳和氢，并在约800℃至约1200℃的温度下退火硼和碳膜。