公开(公告)号：WO1997004393A1

公开(公告)日：1997-02-06

申请号：PCT/US1996011801

申请日：1996-07-16

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BISHOP, Peter, B.

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F2212/401 ,  Y10S707/99953 ,  Y10S707/99955

Abstract: A file access history attribute may be encoded and stored with a file in a computer memory. The file access history attribute may provide information as to the date of most recent access and the level of access on which date. In addition, the file access history attribute may provide information concerning recent file history (e.g., previous nine days), quarterly history (e.g., 80 days preceding the previous nine days), as well as long-term history (e.g., beyond the 80 day period). The encoding technique of the present invention may compress file access history information into a compact file access history attribute (e.g., six to twelve bytes). Disk caching software, for maintaining files in a hard drive of a local computer coupled to a network, may utilize the file access history attribute in deciding which files are to be stored in the local hard drive and which should be migrated to network storage or archive. A file history maintenance program may operate as a background job to periodically update file access history relative to a known maintenance start date.

Abstract translation: 可以将文件访问历史属性编码并存储在计算机存储器中的文件中。 文件访问历史属性可以提供关于最近访问的日期和在哪个日期的访问级别的信息。 此外，文件访问历史属性可以提供关于最近的文件历史（例如，前九天），季度历史（例如，前九天之前的80天）以及长期历史（例如，超过80天）的信息 日期）。 本发明的编码技术可以将文件访问历史信息压缩成压缩文件访问历史属性（例如，6到12个字节）。 磁盘缓存软件，用于维护耦合到网络的本地计算机的硬盘驱动器中的文件，可以利用文件访问历史属性来决定将哪些文件存储在本地硬盘驱动器中，哪些文件应迁移到网络存储或存档 。 文件历史维护程序可以作为后台作业运行，以相对于已知维护开始日期定期更新文件访问历史。

公开(公告)号：WO1996032674A2

公开(公告)日：1996-10-17

申请号：PCT/US1996005106

申请日：1996-04-11

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  NEMAZIE, Siamack

IPC: G06F03/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1068 ,  G11C7/103

Abstract: In storage subsystems such as winchester disk, blocks of sequential data corresponding to sectors are concurrently accessed by the disk and the host. Semiconductor memory devices for storing block data are often utilized as storage location for sectors of data read or written to the disk and the host. Application of a semiconductor memory which increases the effective transfer rate of the system is highly desirable particularly in disk storage systems. A semiconductor memory for use in disk storage applications where information is transferred in blocks of data is hereby disclosed. Specifically, the memory includes a main memory configured as a random access memory array having rows and columns, each row having a plurality of n-bit words, a secondary memory having a data register file, first and second parallel-by-bit interfaces and a transferring circuit for transferring data between the main and secondary memories. Access to the main memory through a first interface is achieved independently of accesses to the secondary memory through a second interface thereby allowing concurrent accesses. Accordingly, concurrent and independent semiconductor memory accesses by any two utilization device located externally to the memory such as a host, a disk sequencer, an ECC logic or a microcontroller is performed without corruption of the data. Further included in the secondary memory is a mask register file for maintaining the integrity of adjacent blocks of data when a block or sector of data having more words than the number of words in a row of the main memory is affected.

Abstract translation: 在诸如温彻斯特磁盘的存储子系统中，对应于扇区的顺序数据块由磁盘和主机同时访问。 用于存储块数据的半导体存储器件通常用作读取或写入盘和主机的扇区的存储位置。 提高系统有效传输速率的半导体存储器的应用是非常需要的，特别是在磁盘存储系统中。 特此公开了一种用于在数据块传送信息的磁盘存储应用中的半导体存储器。 具体地说，存储器包括被配置为具有行和列的随机存取存储器阵列的主存储器，每行具有多个n位字，具有数据寄存器文件的辅存储器，第一和第二并行比特接口以及 用于在主存储器和次存储器之间传送数据的传送电路。 独立于通过第二接口对辅助存储器的访问实现通过第一接口访问主存储器，从而允许并发访问。 因此，在不破坏数据的情况下，执行位于存储器诸如主机，磁盘定序器，ECC逻辑或微控制器之外的任何两个利用装置的并发且独立的半导体存储器访问。 辅助存储器中还包括一个掩码寄存器文件，用于当具有比主存储器的一行中的字数更多的字数据的数据块或扇区受到影响时，保持相邻数据块的完整性。

公开(公告)号：WO1996018988A2

公开(公告)日：1996-06-20

申请号：PCT/US1995015847

申请日：1995-12-06

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  SHARMA, Sudhir

IPC: G09G00/00

CPC classification number: G09G5/14 ,  G09G5/397

Abstract: Display control circuitry is provided which includes a frame buffer (104) having a plurality of memory spaces (301) each for storing a block of display data. Circuitry (200) is provided for generating display position data representing a position on a display screen corresponding to a current display pixel being generated. For each memory space (301), a window control circuit (201) is provided for controlling the transfer of a block of data from the given memory space (301) to a selected window on the display screen. Each window control circuit (201) includes first registers (205, 206) for storing data defining horizontal boundaries of the window, second registers (210, 211) for storing data defining vertical boundaries of the window, and circuitry (207, 208, 209, 212, 213, 214) for comparing the display position data with data stored in the first and second registers and generate an enable signal when the position on the screen of the current pixel is within the window boundaries. Memory control circuitry (300, 302) is provided for retrieving data from the memory space (301) selected in response to the enable signals received from the window control circuits (201).

Abstract translation: 提供了显示控制电路，其包括具有多个存储空间（301）的帧缓冲器（104），每个存储空间用于存储显示数据块。 提供电路（200），用于产生表示与正在生成的当前显示像素对应的显示屏幕上的位置的显示位置数据。 对于每个存储器空间（301），提供窗口控制电路（201），用于控制从给定存储器空间（301）到显示屏幕上的选定窗口的数据块的传送。 每个窗口控制电路（201）包括用于存储定义窗口水平边界的数据的第一寄存器（205,206），用于存储定义窗口垂直边界的数据的第二寄存器（210,211），和电路（207,208,209 ，212,213,214），用于将显示位置数据与存储在第一和第二寄存器中的数据进行比较，并且当当前像素的屏幕上的位置在窗口边界内时产生使能信号。 提供存储器控制电路（300,302），用于从响应于从窗口控制电路（201）接收的使能信号选择的存储器空间（301）中检索数据。

公开(公告)号：WO1996008874A1

公开(公告)日：1996-03-21

申请号：PCT/US1995011988

申请日：1995-09-15

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: H03M13/00

CPC classification number: H03M13/00 ,  H03M13/01 ,  H03M13/09

Abstract: EDC/CRC checker (70) performs an EDC/CRC check as a block of data is being corrected during a correction pass, thereby obviating buffer access for EDC/CRC purposes subsequent to block correction. During the correction pass, an EDC/CRC sum is accumulated which, upon completion of the pass of the block, is zero EDC/CRC bytes in the block confirm that the block has been corrected. During the single correction pass of the block, bytes of an uncorrected, most-recent codeword are added to the accumulated sum. Bytes of a previous codeword which have a byte synchronization relationship with the byte of the most-recent codeword are corrected (if necessary), and (when correction occurs) error pattern factors including error patterns used to correct the bytes of the previous codeword are also added to the accumulated sum. In the illustrated embodiment, the block is conceptualized as having columns of codewords and the byte synchronization relationship is such that when an uncorrected byte is being accumulated, correction occurs for a corresponding byte of a next previous codeword. Various embodiments of the invention are capable of handling a plurality of codewords simultaneously.

Abstract translation: EDC / CRC校验器（70）在校正通过期间正在校正数据块时执行EDC / CRC校验，从而在块校正之后消除用于EDC / CRC目的的缓冲器访问。 在校正通过期间，累加EDC / CRC和，其在块的通过完成时为零，该块中的EDC / CRC字节确认该块已被校正。 在块的单次校正通过期间，未校正的最近的码字的字节被加到累积和。 纠正与最近的码字的字节具有字节同步关系的先前码字的字节（如果需要的话），并且（当发生校正时）包括用于校正先前码字的字节的错误模式的错误模式因子也是 加到累计金额 在所示实施例中，块被概念化为具有码字列，并且字节同步关系使得当未校正的字节正在被累积时，针对下一个前一码字的对应字节进行校正。 本发明的各种实施例能够同时处理多个码字。

公开(公告)号：WO1996008873A1

公开(公告)日：1996-03-21

申请号：PCT/US1995011987

申请日：1995-09-15

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: H03M13/00

CPC classification number: G06F7/726 ,  G06F11/10 ,  G06F11/1004 ,  G11B20/10527 ,  G11B20/18 ,  G11B20/1813 ,  G11B20/1833 ,  H03M13/00 ,  H03M13/05 ,  H03M13/15 ,  H03M13/151 ,  H03M13/35

Abstract: An error correction system operates in two modes: (1) a two-phased mode for correcting computer data having pointers; and (2) a subcode mode for correcting subcode packs included with audio digital data. During the two-phased mode for correcting computer data with pointers, a generator (20), calculator (30), and corrector (60) are each operated during two phases. During a first phase (known as PTR-TIME) the generator (20) generates one or two multi-bit buffer-obtained pointers ( alpha = PO, alpha = P1) for the most-recent codeword while the calculator (30) uses syndromes (S0, S1) generated by generator (20) for a previous codeword CWn-1 to generate one or two error patterns (E0, E1) for the previous codeword. During a second phase (shown as DATA-TIME), the generator (20) generates syndromes (S0, S1) for the most-recent codeword CWn while the calculator (30) performs mathematical operation(s) with respect to any multi-bit buffer-obtained pointers (i.e., P0, P1) for the most-recent codeword CWn. In the subcode mode, the error correction system attempts to perform correction with a subcode pack. In correcting subcodes, the system first generates differing sets of subcode syndromes with respect to differing portions of the pack. After generation of the subcode syndromes, the system controller (10) analyzes the subcode syndromes and applies differing correction strategies in accordance with the analysis. In view of the differing field lengths of the computer data and the subcodes, the syndrome generator (20) is selectively configurable for selection of differing feedback paths (e.g., feedback multipliers).

Abstract translation: 纠错系统以两种模式操作：（1）用于校正具有指针的计算机数据的两相模式; 和（2）用于校正包括在音频数字数据中的子码包的子码模式。 在用指针校正计算机数据的两相模式期间，发生器（20），计算器（30）和校正器（60）分别在两个阶段期间操作。 在第一阶段（称为PTR-TIME）期间，生成器（20）为最近的码字生成一个或两个多位缓冲器获得的指针（α = PO，αL1= P1），而 计算器（30）使用由发生器（20）生成的用于先前码字CWn-1的综合征（S0，S1）来产生用于先前码字的一个或两个错误模式（E0，E1）。 在第二阶段（显示为DATA-TIME）期间，发生器（20）为最近的码字CWn产生校正子（S0，S1），而计算器（30）相对于任何多位 用于最近的码字CWn的缓冲器获得的指针（即，P0，P1）。 在子代码模式中，错误校正系统尝试用子代码包执行校正。 在校正子码中，系统首先针对包的不同部分生成不同的子码综合征集合。 在产生子代码综合征之后，系统控制器（10）分析子代码综合征，并根据分析应用不同的校正策略。 考虑到计算机数据和子代码的不同的场长度，校正子发生器（20）可选择性地被配置用于选择不同的反馈路径（例如，反馈乘法器）。

公开(公告)号：WO1996008810A1

公开(公告)日：1996-03-21

申请号：PCT/US1995012088

申请日：1995-09-11

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

IPC: G09G01/16

CPC classification number: G11C7/1036

Abstract: A memory (200) is provided which includes a plurality of self-contained memory units (201) for storing data. A plurality of shift registers (211) are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units (201). Interconnection circuitry (212) is coupled to a parallel data port of each of the shift registers. Control circuitry (208, 213) is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry (212) via the shift register (211) coupled to the selected memory unit (201).

Abstract translation: 提供了一种存储器（200），其包括用于存储数据的多个独立存储单元（201）。 提供了多个移位寄存器（211），每个移位寄存器包括耦合到相应的一个独立存储单元（201）的数据端口的第一并行端口。 互连电路（212）耦合到每个移位寄存器的并行数据端口。 提供控制电路（208,213），其可操作以经由耦合到所选择的存储器单元（201）的移位寄存器（211）来控制存储器单元和互连电路（212）中的所选择的一个之间的数据交换。

公开(公告)号：WO1996005597A1

公开(公告)日：1996-02-22

申请号：PCT/US1995010446

申请日：1995-08-15

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RUNAS, Michael, E.

IPC: G11C07/00

CPC classification number: G11C7/1021 ,  G11C7/00

Abstract: Memory circuitry (200) is provided which includes first and second banks of memory cells (201a, 201b) arranged in rows and columns. Row decoder circuitry (210) is included for selecting a row in at least one of the memory banks (201) in response to a row address. Row address circuitry (208, 209, 215) is provided for presenting a sequence of the row addresses to the row decoder circuitry (210) in response to a single row address provided at an address port to memory circuitry (200). Column decoder circuitry (213) is further included for selecting a column in each of the banks (201) in response to a column address. Column address circuitry (211, 212, 215) presents a sequence of the column addresses to the column decoder circuitry (213) in response to a single column address received at the address port to memory circuitry (200).

Abstract translation: 提供存储器电路（200），其包括以行和列排列的第一和第二存储单元组（201a，201b）。 包括行解码器电路（210），用于响应于行地址来选择至少一个存储体（201）中的行。 行地址电路（208,209,215）被提供用于响应于在存储器电路（200）的地址端口处提供的单行地址，向行解码器电路（210）呈现行地址的序列。 还包括列解码器电路（213），用于响应于列地址来选择每个存储体（201）中的列。 列地址电路（211,212,215）响应于在地址端口处接收到存储器电路（200）的单列地址，向列解码器电路（213）呈现列地址的序列。

公开(公告)号：WO1995030988A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005761

申请日：1995-05-08

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

IPC: G11C11/00

CPC classification number: G11C29/80 ,  G11C7/1006 ,  G11C11/005 ,  G11C29/81 ,  G11C29/88

Abstract: A processing device (107) is provided disposed on a single chip which includes a controller (103) and a memory (104). The controller (103) is coupled to an address bus (202) and a data bus (204). The memory (103) includes a plurality of independently addressable blocks (200) of memory cells, each block (200) coupled to the address bus (202) and having a selected number of output lines coupled to the data bus (204). The controller (103) accesses a location of the selected number of memory cells of a selected one of the blocks (200) through an address presented on the address bus (202).

Abstract translation: 设置在包括控制器（103）和存储器（104）的单个芯片上的处理设备（107）。 控制器（103）耦合到地址总线（202）和数据总线（204）。 存储器（103）包括存储器单元的多个可独立寻址的块（200），每个块（200）耦合到地址总线（202）并且具有耦合到数据总线（204）的选定数量的输出线。 控制器（103）通过地址总线（202）上呈现的地址访问所选择的一个块（200）的选定数量的存储器单元的位置。

公开(公告)号：WO1995024038A1

公开(公告)日：1995-09-08

申请号：PCT/US1995002609

申请日：1995-03-03

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  NEMAZIE, Siamack ,  SCHADEGG, John

IPC: G11B20/18

CPC classification number: G11B20/1883 ,  G11B20/1252 ,  G11B20/1258 ,  G11B2020/1234 ,  G11B2020/1282 ,  G11B2020/1284 ,  G11B2220/20

Abstract: Defect management for automatic track processing without an ID field processes defect information for a track on a magnetic media within a disk drive system. A system which uses any method of defect management including linear replacement, sector slipping, cylinder slipping or segment slipping, can be supported. A physical sector number for each sector is translated to a logical sector number relating to the order of data on a track. This translation of the physical sector number to a logical sector number for automatic track processing can be accomplished using any one of three methods: 1) a track defect table can be built in the buffer RAM; 2) the defect information can be written in the header of every sector; or 3) a system FIFO, located in the onboard logic, can be used to manage the defect list. In the second method, the header subfield comprises four defect records. In the third method, if there are more defect records for the track than will fit in the FIFO, then the first and second banks are each loaded while the other is being processed in a ping-pong manner until all of the defect records for the track have been processed. A defect record includes a physical sector number of the defective sector, an offset number and a flag indicating whether or not the defective sector has been slipped. Defect flags are automatically generated by the system for each defective sector.

Abstract translation: 在没有ID字段的情况下自动跟踪处理的缺陷管理处理磁盘驱动器系统中的磁性介质上的轨道的缺陷信息。 可以支持使用任何缺陷管理方法的系统，包括线性替换，扇形滑动，气缸滑动或段滑动。 每个扇区的物理扇区号被转换为与轨道上的数据顺序有关的逻辑扇区号。 将物理扇区号转换为用于自动轨道处理的逻辑扇区号可以使用以下三种方法之一完成：1）轨道缺陷表可以内置在缓冲RAM中; 2）缺陷信息可以写在每个扇区的标题中; 或3）位于板载逻辑中的系统FIFO可用于管理缺陷列表。 在第二种方法中，标题子字段包括四个缺陷记录。 在第三种方法中，如果轨道的缺陷记录多于符合FIFO的缺陷记录，则第一和第二组各自被加载，而另一个正在以乒乓方式处理，直到所有的缺陷记录为 轨道已经被处理。 缺陷记录包括缺陷扇区的物理扇区号，偏移号和指示缺陷扇区是否已滑动的标志。 缺陷扇区由系统自动生成。

公开(公告)号：WO1995012921A1

公开(公告)日：1995-05-11

申请号：PCT/US1994012138

申请日：1994-10-18

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: H03M13/00

CPC classification number: H03M13/091 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1068 ,  G11B20/1833 ,  H03M13/09 ,  H03M13/35

Abstract: One-stage and two-stage CRC generation systems (400, 600) feature a CRC generator/checker (700) comprising a segmenter (710) of an input data stream into substreams, a circuit (712) forming a linear combination of the substreams and generating CRC bytes therefrom, and a checker (714) comparing the CRC bytes with previously generated CRC bytes. The two-stage system (600) includes a first CRC generator/checker (601) generating primary CRC bytes, a memory (602) receiving the input data and the primary CRC bytes, and a second CRC generator/checker (603) generating verification CRC bytes for comparison with the primary CRC bytes to check the input data after retrieval from the memory (602) and before input to an encoder (604). The second CRC generator/checker (603) can optionally apply some of the verification CRC bytes to the encoder (604) for use as secondary CRC bytes. The number of CRC bytes outputted by the CRC generator/checkers (601, 603) is programmable.

Abstract translation: 一级和两级CRC生成系统（400,600）具有CRC生成器/检查器（700），其包括输入数据流的分段器（710），进入子流，电路（712）形成子流的线性组合 以及从其生成CRC字节;以及检查器（714），将CRC字节与先前产生的CRC字节进行比较。 两级系统（600）包括：生成主CRC字节的第一CRC生成器/检查器（601），接收输入数据和主CRC字节的存储器（602）;以及生成验证的第二CRC生​​成器/检查器（603） CRC字节用于与主CRC字节进行比较，以在从存储器（602）检索并在输入到编码器（604）之前检查输入数据。 第二CRC生​​成器/检查器（603）可以可选地将一些验证CRC字节应用于编码器（604）以用作次级CRC字节。 由CRC发生器/检查器（601,603）输出的CRC字节的数量是可编程的。