公开(公告)号：WO1998029838A1

公开(公告)日：1998-07-09

申请号：PCT/US1997023910

申请日：1997-12-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  WILDE, Daniel

IPC: G06T15/10

CPC classification number: G06T15/04

Abstract: A process and implementing computer system for graphics applications in which polygon information, including transparency, color and other polygon characteristics, is organized, stored and transferred in terms of areas or tiled blocks of information in a matrix configuration. The polygon bytes of texel information are organized in an exemplary 8X8 matrix row and column format in the graphics subsystem for improved cache-hit efficiency and translated to and from the linear addressing scheme of a host storage device when the host storage is accessed to refill the graphics cache. The bytes comprising the memory tiles of polygon information are arranged such that a complete tile of information is transferred in one burst-mode host memory access to minimize normal multi-line access arbitration and other typical access delays.

Abstract translation: 用于图形应用的处理和实现计算机系统，其中根据矩阵配置中的面积或平铺的信息块来组织，存储和传送多边形信息，包括透明度，颜色和其他多边形特征。 纹理信息的多边形字节以图形子系统中的示例性8×8矩阵行和列格式组织，用于改进的高速缓存命中效率，并且当主存储器被访问以重新填充主机存储设备时被转换成主机存储设备的线性寻址方案 图形缓存。 包括多边形信息的存储器片的字节被布置成使得在一个突发模式主机存储器访问中传送完整的信息块，以最小化正常的多线路访问仲裁和其他典型的访问延迟。

公开(公告)号：WO1998029836A3

公开(公告)日：1998-07-09

申请号：PCT/US1997024290

申请日：1997-12-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  VASWANI, Guatam, P. ,  LARSON, Michael ,  DYE, Thomas, A. ,  WILDE, Daniel

IPC: G06T15/10

公开(公告)号：WO1998025272A1

公开(公告)日：1998-06-11

申请号：PCT/US1997023830

申请日：1997-12-03

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

IPC: G11C11/409

CPC classification number: G11C7/06 ,  G11C11/4091

Abstract: An amplifier (300) includes a differential pair of transistors (307a, 307b). A third transistor (306) controls current through transistors (307a, 307b) of the differential pair in response to a stepped control signal.

Abstract translation: 放大器（300）包括差分对晶体管（307a，307b）。 第三晶体管（306）响应于阶梯式控制信号控制通过差分对的晶体管（307a，307b）的电流。

公开(公告)号：WO1998011532A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016140

申请日：1997-09-10

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  JENKINS, Michael

IPC: G10H07/02

CPC classification number: G10H1/125 ,  G10H7/02 ,  G10H2210/205 ,  G10H2210/281 ,  G10H2210/305 ,  G10H2240/056 ,  G10H2240/145 ,  G10H2250/061 ,  G10H2250/105 ,  G10H2250/121

Abstract: A variable sample rate approximation technique is used for coding and recreating musical signals in a wavetable synthesizer. Many sounds inherently include one large fast transfer of energy followed by vibrations that dampen over time so that the bandwidth requirement of a musical sound is reduced with passing time. Using the variable sample rate approximation technique, musical sounds are classified into two categories, sustaining sounds and percussive sounds. A sustaining instrument creates a noisy stimulus then sustains the sound created by the noisy stimulus. A percussive instrument is also a noisy source and generates a sound signal having high frequencies that decay rapidly while sustaining instruments sustain at all frequencies nearly equally. The sustaining and percussive instruments have substantially different waveform characteristics but present similar conditions with respect to memory reduction. Similarities between the acoustical characteristics of sustaining sounds and percussive sounds are exploited using a variable sampling rate technique to substantially reduce the memory budget of a wavetable synthesizer.

Abstract translation: 可变采样率近似技术用于在波形合成器中编码和再现音乐信号。 许多声音固有地包括一个大的快速的能量传递，随后随着时间的推移而衰减的振动，使得音乐声音的带宽需求随着时间的流逝而减少。 使用可变采样率近似技术，音乐声音分为两类，维持声音和打击乐。 持续的工具产生嘈杂的刺激，然后维持由嘈杂的刺激产生的声音。 打击乐器也是噪音源，并产生具有高频衰减的声音信号，同时维持仪器在所有频率下几乎保持平等。 持续和打击乐器具有基本上不同的波形特性，但在存储器减少方面存在相似的条件。 使用可变采样率技术来利用持续声音和打击乐声音的声学特性之间的相似性，以显着降低波形合成器的存储器预算。

公开(公告)号：WO1998011531A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016143

申请日：1997-09-10

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  SCOTT, Jeffrey, W.

IPC: G10H01/12

CPC classification number: G10H1/125 ,  G10H2210/225 ,  G10H2240/056 ,  G10H2250/061 ,  G10H2250/121 ,  Y10S84/09

Abstract: A nonperiodic waveform is forced to a periodic character to facilitate looping of the waveform without introducing audible, and thus objectionable, sound artifacts. Nonperiodic waveforms are typically nonperiodic due to the presence of nonharmonic high frequency spectral components. In time, the high frequency components decay faster than low frequency components and looping of the waveform is facilitated. A loop forcing process and loop forcing filter facilitate looping of a nonperiodic waveform by accelerating the removal of the nonperiodic high frequency components. A loop forcing filter accelerates the removal of nonperiodic high frequency components using a comb filter having a frequency selectivity that varies in time.

Abstract translation: 非周期性波形被强制为周期性字符以便于波形的循环，而不引入可听见的，因此令人反感的声音伪影。 由于存在非谐波高频谱分量，非周期波形通常是非周期性的。 随着时间的推移，高频分量比低频分量衰减得更快，波形的循环变得容易。 环路强制过程和环路强制滤波器通过加速去除非周期性高频分量来促进非周期波形的循环。 环路强制滤波器使用具有随时间变化的频率选择性的梳状滤波器来加速非周期性高频分量的去除。

公开(公告)号：WO1997004457A2

公开(公告)日：1997-02-06

申请号：PCT/IB1996001001

申请日：1996-07-12

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

IPC: G11C11/407

CPC classification number: G11C7/1042 ,  G11C7/1039 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076

Abstract: A dynamic random access memory device (200) includes circuitry (202) for generating a plurality of internal row address strobes. A plurality of memory banks (201) are included, each having an array (203) of dynamic random access cells and associated dynamic control circuitry. A first one of the memory banks (201) enters precharge in response to a precharged cycle of a first one of the internal row address strobes. Simultaneoulsy, a second one of the banks (201) enters an active cycle in response to an active cycle of a second one of the internal address strobes.

Abstract translation: 动态随机存取存储器件（200）包括用于产生多个内部行地址选通的电路（202）。 包括多个存储体（201），每个具有动态随机存取单元的阵列（203）和相关联的动态控制电路。 存储器组（201）中的第一个响应于内部行地址选通中的第一个的预充电周期而进入预充电。 同时脉冲，第二组（201）响应于第二个内部地址选通的有效周期而进入有效周期。

公开(公告)号：WO1997004446A2

公开(公告)日：1997-02-06

申请号：PCT/IB1996001128

申请日：1996-07-12

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ROMANO, Paul, M. ,  SUPINO, Louis

IPC: G11B05/48

CPC classification number: G11B5/59683 ,  G11B5/5547 ,  G11B2005/0016

Abstract: A sliding mode controller for controlling the motion of a magnetoresistive (MR) read head actuated by a voice coil motor over a rotating magnetic disk storage medium. The magnetic disk comprises a plurality of concentric data tracks recorded thereon wherein each data track comprises user data and servo data. The sliding mode controller operates by multiplying a head position error phase state and a head position error velocity phase state by respective switching gains to force the phase states to follow a predetermined phase state trajectory. The phase state trajectory can be defined by a single linear segment, a variable linear segment, multiple linear segments over the entire region of excursion, or optimum parabolic acceleration and deceleration segments. Switching logic, responsive to the phase states and a trajectory segment value sigma , switches between positive and negative feedback gains to drive the phase states toward a current trajectory segment. A sigma processing block monitors the phase states to determine when to switch from a current trajectory segment to the next trajectory segment. The resulting servo control system is relatively inexpensive to implement in either software or hardware, and it is substantially insensitive to parametric changes, external load disturbances, and nonlinearities inherent in controlling MR read heads. Further, it does not require notch filters commonly used in conventional linear controllers to compensate for mechanical resonances.

Abstract translation: 一种滑动模式控制器，用于控制由音圈电机在旋转磁盘存储介质上驱动的磁阻（MR）读头的运动。 磁盘包括记录在其上的多个同心数据轨道，其中每个数据轨道包括用户数据和伺服数据。 滑动模式控制器通过将头部位置误差相位状态和头部位置误差速度相位状态乘以相应的切换增益来操作，以迫使相位状态遵循预定的相位状态轨迹。 相位状态轨迹可以由单个线性段，可变线性段，整个移动区域上的多个线性段或最佳抛物线加速和减速段来定义。 响应于相位状态和轨迹段sigma的开关逻辑在正和负反馈增益之间切换以将相位状态驱动到当前轨迹段。 西格玛处理块监视相位状态以确定何时从当前轨迹段切换到下一轨迹段。 所得到的伺服控制系统在软件或硬件中实现相对便宜，并且对于控制MR读取头固有的参数变化，外部负载扰动和非线性实质上不敏感。 此外，它不需要通常用于常规线性控制器的陷波滤波器来补偿机械谐振。

公开(公告)号：WO1997002533A1

公开(公告)日：1997-01-23

申请号：PCT/IB1996000729

申请日：1996-07-03

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  KENNY, John, D. ,  SHAH, Pranay, D.

IPC: G06F13/40

CPC classification number: G06F13/4054

Abstract: A bridge and a method for interfacing a plurality of buses with which the bridge provides electrical isolation between the buses but is transparent so that the plurality of buses is viewed by software as a single logical bus. Transaction cycles initiated on one bus are reflected on the other bus. A speculative start of a transaction cycle on a secondary bus immediately after the transaction cycle has been started on the first bus provides a significant savings in time to complete transactions in which the target of the transaction is on the secondary bus.

Abstract translation: 用于与多个总线接口的桥接器和方法，桥接器在总线之间提供电隔离，但是是透明的，使得多个总线被软件视为单个逻辑总线。 在一条总线上启动的事务周期反映在另一条总线上。 在第一个总线上开始交易周期之后，辅助总线上的交易周期的推测开始提供了大量的时间来完成交易目标在次级总线上的交易。

公开(公告)号：WO1996027882A1

公开(公告)日：1996-09-12

申请号：PCT/US1996002831

申请日：1996-03-01

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  NEMAZIE, Siamack ,  SCHADEGG, John

IPC: G11B20/18

CPC classification number: G11B20/1883 ,  G11B2020/1234 ,  G11B2220/20

Abstract: Defect management for automatic track processing without an ID field, processes defect information for a track on a magnetic media within a disk drive system. A system which uses any method of defect management including linear replacement, sector slipping, cylinder slipping or segment slipping, can be supported. A physical sector number for each sector is translated to a logical sector number relating to the order of data on a track. This translation of the physical sector number to a logical sector number for automatic track processing can be accomplished using any one of three methods: 1) a track defect table can be built in the buffer RAM; 2) the defect information can be written in the header of every sector; or 3) a system FIFO, located in the onboard logic, can be used to manage the defect list. The first and third methods support an ID_less format wherein the data field does not contain a header subfield and information for sector identification is maintained by the disk drive system. In the second method, the header subfield comprises four defect records. In the third method, if there are more defect records for the track than will fit in the FIFO, then after initialization and loading the first and second banks of the FIFO by the drive microprocessor, the first and second banks are each loaded by the drive microprocessor while the other is being processed, in a ping-pong manner, until the track processing is complete. A defect record includes a physical sector number of the defective sector, an offset number and a flag indicating whether or not the defective sector has been slipped. The defect record may be either a fixed two byte entry or may be of a user defined number of bytes. Defect flags are automatically generated by the system for each defective sector.

Abstract translation: 缺少ID字段的自动跟踪处理的缺陷管理，处理磁盘驱动器系统中磁性介质上的磁道的缺陷信息。 可以支持使用任何缺陷管理方法的系统，包括线性替换，扇形滑动，气缸滑动或段滑动。 每个扇区的物理扇区号被转换为与轨道上的数据顺序有关的逻辑扇区号。 将物理扇区号转换为用于自动轨道处理的逻辑扇区号可以使用以下三种方法之一完成：1）轨道缺陷表可以内置在缓冲RAM中; 2）缺陷信息可以写在每个扇区的标题中; 或3）位于板载逻辑中的系统FIFO可用于管理缺陷列表。 第一和第三种方法支持ID_less格式，其中数据字段不包含标题子字段，并且用于扇区标识的信息由磁盘驱动器系统维护。 在第二种方法中，标题子字段包括四个缺陷记录。 在第三种方法中，如果轨道的缺陷记录多于符合FIFO的缺陷记录，则在通过驱动微处理器初始化和加载FIFO的第一和第二组之后，第一和第二组各自被驱动器加载 微处理器，而另一个正在以乒乓方式处理，直到轨道处理完成。 缺陷记录包括缺陷扇区的物理扇区号，偏移号和指示缺陷扇区是否已滑动的标志。 缺陷记录可以是固定的两字节条目，也可以是用户定义的字节数。 系统为每个缺陷扇区自动生成缺陷标志。

公开(公告)号：WO1996024137A2

公开(公告)日：1996-08-08

申请号：PCT/US1996001351

申请日：1996-01-31

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

IPC: G11C11/413

CPC classification number: G11C8/10

Abstract: A memory device (200) is provided which includes an array (202) of rows and columns of memory cells (201). Row decoder circuitry (206) is provided for selecting a given row of cells (201) for access. Circuitry (208, 209) is included for providing a selected one of a plurality of supply voltages to the row decoder circuitry (206), a first positive voltage provided during an active state of the row decoder circuitry (206) and a second positive voltage provided during an inactive state of the row decoder circuitry (206).

Abstract translation: 提供了一种存储器件（200），其包括存储器单元（201）的行和列的阵列（202）。 行解码器电路（206）被提供用于选择用于访问的给定行单元（201）。 包括电路（208,209），用于向行解码器电路（206）提供多个电源电压中选择的一个，在行解码器电路（206）的有效状态期间提供的第一正电压和第二正电压 在行解码器电路（206）的无效状态下提供。