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公开(公告)号：JPH0945075A
公开(公告)日：1997-02-14
申请号：JP18881895
申请日：1995-07-25
Applicant: HITACHI LTD
Inventor： OGURA MAKOTO , KUROSAWA KENICHI , MORIOKA MICHIO , ISHIKAWA SUKETAKA
IPC: G11C11/41 , G06F12/00 , G06F13/16 , G11C11/401 , G11C11/407
Abstract: PROBLEM TO BE SOLVED: To expedite the latency by disposing no logic gate between a memory cell and a memory controller, thereby enabling one cycle transfer from the cell to the controller. SOLUTION: When an address switch controller 2 selects a memory card 7 connected with a memory address bus 33 and a memory data bus 29, it connects the buses 22, 4 via a semiconductor switch 5 by using a semiconductor switch control signal 10. Then, the controller 2 outputs the signal necessary for row and column addresses and a memory access signal to the bus 4, and the card 7 outputs data to the bus 19 after a predetermined cycle. The controller 2 connects the buses 18, 19 via the switch 17 by a semiconductor control signal 11 before one cycle when the card 7 outputs the data. Thus, the switches 5, 17 formed of MOS transfer gates are disposed between the card 7 and a memory controller 1 to make the logic gate unstable to transfer one cycle from the card 7 to the controller 1.
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公开(公告)号：JPH08335933A
公开(公告)日：1996-12-17
申请号：JP14289195
申请日：1995-06-09
Applicant: HITACHI LTD
Inventor： KASHIWAGI KENJI , YAMAGIWA AKIRA , INOUE MASAO , ISHIKAWA SUKETAKA , MIYAZAKI YOSHIHIRO , TAKATANI SOICHI , MATSUDA KOJI , YAMAGUCHI SHINICHIRO , KUROSAWA KENICHI
Abstract: PURPOSE: To switch a clock signal source without giving effect on a clock output by providing a PLL circuit to the post stage of a changeover circuit. CONSTITUTION: A PLL circuit 9 is operated based on a reference signal inputted by a phase comparator 6. The phase comparator 6 outputs the phase difference between the reference signal and a feedback signal from a voltage controlled oscillator 8 as an error. A loop filter 7 eliminates a high frequency component included in the output of the phase comparator 6 and outputs only a DC component in the error signal. The voltage controlled oscillator 8 corrects its oscillating signal in matching with the output of the loop filter 7. The PLL circuit 9 matches the phase and the frequency of the feedback signal with those of the reference signal at an input section of the phase comparator 6 by repeating the operation above. Thus, the operation is continued without notifying the stop of a clock signal source 1 and changeover of clock signal sources 1, 2.
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93.发明专利
公开(公告)号：JPH08190442A
公开(公告)日：1996-07-23
申请号：JP306795
申请日：1995-01-12
Applicant: HITACHI LTD
Inventor： MATSUDA KOJI , TAKATANI SOICHI , MIYAZAKI YOSHIHIRO , KUROSAWA KENICHI , YAMAGUCHI SHINICHIRO , ISHIKAWA SUKETAKA , YAMAGIWA AKIRA , INOUE MASAO , KASHIWAGI KENJI
IPC: G06F1/04
Abstract: PURPOSE: To make an output clock uninterruptible when doubled clocks are switched and to prevent respective processors from malfunctioning by selecting the clock of a clock generation source to be used in common to plural threads that perform processes synchronously. CONSTITUTION: Clock selecting devices 3-1 and 3-2 having received an external signal switch a clock generation source to be used by the respective threads in common from a clock generation source which gets out of order, to a clock generation source, so that the clock to be used is switched from a clock generation source 1-1 to a clock generation source 1-2. Clock phase adjusting devices 4-1 and 4-2 normally adjust the phase of the output clock from the phase of a clock before switching to the phase of a clock after the switching gradually for plural cycles when a clock in phase with an input clock is outputted or when a selecting means switches the clock to another normal clock owing to the fault of the clock generation source. Consequently, processing units 5-1 and 5-2 are supplied normally with in-phase clocks from the same clock generation source.
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公开(公告)号：JPH07262776A
公开(公告)日：1995-10-13
申请号：JP4823894
申请日：1994-03-18
Applicant: HITACHI LTD
Inventor： KUROSAWA KENICHI , OGURA MAKOTO , MORIOKA MICHIO , NAKAMIGAWA TETSUAKI , ISHIKAWA SUKETAKA
IPC: G11C11/417 , G06F13/16 , G11C7/10 , G11C11/409
Abstract: PURPOSE:To make the access at a high speed by arranging a Schottky diode between a semiconductor memory and a memory bus wiring and controlling a reverse bias voltage. CONSTITUTION:A signal line 1-4 is connected to a memory bus signal line 4-1 through a Schottky diode 1-3. The bus signal line 4-1 is connected to a voltage Vtt through a terminal resistor 4-2. Thus, when the semiconductor memory or a memory controller does not drive a memory bus, the bus signal line 4-1 as well as the signal line 1-4 becomes a high level. When the signal line 1-4 becomes high level once, a reverse bias voltage is applied through the Schottky diode 1-3 and the load resistor of a synchronous DRAM 1-1 becomes a cut-off state from the signal line 4-1. The load capacity of the diode 1-3 at the time of applying the reverse bias voltage is very small. Consequently, the load capacity of the semiconductor memory is cut off from the side of the memory bus and a memory system capable of making high-speed access is obtained.
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公开(公告)号：JPH0749733A
公开(公告)日：1995-02-21
申请号：JP19723493
申请日：1993-08-09
Applicant: HITACHI LTD
Inventor： KAMINAGA YASUO , KOBAYASHI YUTAKA , KUROSAWA KENICHI
IPC: G06F3/00
Abstract: PURPOSE:To provide an I/O interface circuit device improved at its speed. CONSTITUTION:In this I/O interface circuit device connecting both ends of a transmission line 3 to terminals capable of receiving terminal voltage through respective terminal resistors 2 and connecting plural integrated circuits 100 respectively including driver/receiver parts and data transmitting/receiving logic circuits 90 for transmitting/receiving data through the line 3 to the line 3, the driver/receiver parts for plural integrated circuits 100 are independently separated from the circuits 100 and constituted in common as a driver/receiver part 200.
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Patent Agency Ranking
公开(公告)号：JPH0744412A
公开(公告)日：1995-02-14
申请号：JP18828093
申请日：1993-07-29
Applicant: HITACHI LTD
Inventor： NAKAMIGAWA TETSUAKI , KUROSAWA KENICHI , MORIOKA MICHIO , OGURO HIROSHI , ISHIKAWA SUKETAKA
IPC: G06F11/16
Abstract: PURPOSE:To realize a computer system in which the deterioration in the performance due to addition of a checker CPU is prevented in the highly reliable computer system adopting multi-CPUs. CONSTITUTION:A master CPU 110, a system controller (SCU) 130 and a comparator 100 are connected to a master processor bus 140. A checker CPU 120 implementing the same processing as that of the master CPU 110 to check the operation of the master CPU 110 is connected to the comparator 100 by a checker processor bus 150. The SCU 130 controls the access from the master CPU 110 to a main storage device 170 and an input output device 190. The comparator 100 compares the processing results outputted from the master and checker CPUs and provides the output of different processing result to the SCU 130 when the processing results differ. Since the data transfer between the master CPU 110 and the SCU 130 does not slow down because the data do not pass through the comparator 100.
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公开(公告)号：JPH0613390B2
公开(公告)日：1994-02-23
申请号：JP15873981
申请日：1981-10-07
Applicant: HITACHI LTD
Inventor： KUZUNUKI SOSHIRO , HIRASAWA KOTARO , KUROSAWA KENICHI , KANEKO TAKASHI
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公开(公告)号：JPH0628180A
公开(公告)日：1994-02-04
申请号：JP19024091
申请日：1991-07-30
Applicant: HITACHI LTD , HITACHI ENG CO LTD
Inventor： MIURA SHUICHI , KUROSAWA KENICHI , NAKAMIGAWA TETSUAKI , HIROSE KENJI
Abstract: PURPOSE:To hit data in the prefetch buffer at the time of an increase or decrease in address by predicting the increase or decrease direction of the address by an address prediction part and prereading data. CONSTITUTION:The prefetch buffet provided between the cache memory and main storage device of a computer system is equipped with a buffet 503 which stores prefetched data and address tags for searching for the data in pairs, a generation part 502 which generates an address in the main storage device for data to be prefetched, a data search part 500 which searches data having an address requested by a CPU among the data stored in the buffer 503, and the address prediction part 501 which determines the address of the data to be prefetched next according to the address requested by the CPU and a history of addresses of past prefetched data in the main storage device.
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公开(公告)号：JPH0524067B2
公开(公告)日：1993-04-06
申请号：JP9820683
申请日：1983-06-02
Applicant: HITACHI LTD
Inventor： YONEDA KENJI , UEJIMA TAKAAKI , KUROSAWA KENICHI , MIURA MASAKI
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公开(公告)号：JPH01229329A
公开(公告)日：1989-09-13
申请号：JP5352388
申请日：1988-03-09
Applicant: HITACHI LTD
Inventor： KUROSAWA KENICHI , SHIMADA MASARU , BANDO TADAAKI , NAKANO TOSHIHIKO , HAYASHI TOSHIHIRO
Abstract: PURPOSE:To speed up a processing requiring all solution sets having heaviest loads in inference and to considerably improve inference speed by generating a means which directly generates solution information, and a means which eliminates a conversion processing. CONSTITUTION:A knowledge processing tool consists of a computer H and a storage device G. Programs which realize respective means for high speed- processing the tool are stored in the area G2 of the device G, and the computer H executes them. For generating solution information sets at high speed, a storage area G5 holding solution information is newly provided, and the execution function of the inference engine is switched to the area G5 after the conditions of the rules are satisfied, whereby the means for directly generating solution information is generated. When the conditions of the rules are satisfied, solution information are directly and sequentially generated in the area G5, not in the form of factual sentences, but of data structure. Solution information having a fact that an attribute value is changed is deleted from the obtained solution information sets at high speed since solution information is data and it does not need conversion.
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