公开(公告)号：JP2011100299A

公开(公告)日：2011-05-19

申请号：JP2009254496

申请日：2009-11-06

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： MATSUMOTO NORITAKE ,  YAMADA TSUTOMU ,  KOBAYASHI EIJI ,  OHASHI AKIHIRO ,  OGURA MAKOTO

IPC: G06F13/38

CPC classification number: G06F11/0766 ,  G06F11/0724 ,  G06F11/076

Abstract: PROBLEM TO BE SOLVED: To provide a technology for ensuring soundness between processors connected to a system bus for serial communication. SOLUTION: A processor 100 is connected to another processor 200 through a system bus L10 including a serial signal communication line L20 and a synchronization signal communication line L30. An arithmetic unit 110 detects an abnormal state in the processor 100, the arithmetic unit 110 outputs an abnormal-state detection report to a synchronization unit 130. The synchronization unit 130 transmits the report to the other processor 200 through the synchronization signal communication line L30. A conversion unit 120 receives parallel communication data from the arithmetic unit 110 through an important signal line L160 instead of a general signal line L150, and converts the received parallel signal to a serial signal, and transmits it to the other processor 200 through the serial signal communication line L20. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于确保连接到用于串行通信的系统总线的处理器之间的良好性的技术。 解决方案：处理器100通过包括串行信号通信线L20和同步信号通信线L30的系统总线L10连接到另一处理器200。 算术单元110检测处理器100中的异常状态，运算单元110将异常状态检测报告输出到同步单元130.同步单元130通过同步信号通信线L30将报告发送到另一个处理器200。 转换单元120通过重要信号线L160而不是一般信号线L150从运算单元110接收并行通信数据，并将所接收的并行信号转换为串行信号，并通过串行信号将其发送到另一个处理器200 通讯线L20。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009005412A

公开(公告)日：2009-01-08

申请号：JP2008247058

申请日：2008-09-26

Applicant: Hitachi Information & Control Solutions Ltd ,  Hitachi Ltd ,  株式会社日立情報制御ソリューションズ ,  株式会社日立製作所

Inventor： ONOZUKA AKIHIRO ,  BANDO AKIRA ,  KOBAYASHI MASAMITSU ,  SHIRAISHI MASAHIRO ,  OGURA MAKOTO ,  UMEHARA TAKASHI ,  KOBAYASHI EIJI ,  FUNAKI SATORU ,  ISHIKAWA MASAKAZU ,  FURUTA YASUYUKI ,  NAKANO AKIHIRO ,  MASUKO NAOYA ,  OZAWA SHOICHI ,  KASAHARA TAKENORI ,  SEKI YUSUKE ,  OTANI TATSUYUKI ,  IWASAKI YU

IPC: H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a communication control device whose transfer performance is not reduced, even when transfer via a line is made, without adding a counter to a plurality of input modules, in a process control system.
SOLUTION: A time counter is provided in a destination communication control device. Furthermore, an input buffer for temporarily storing input data and a time buffer that temporarily stores the time counted value of the time counter are provided in the destination communication control devices. These buffers are simultaneously allowed to update data. The destination communication control device has a means for transmitting a single time value and a plurality of input values. A source communication control device has a means for expanding a single time value into a plurality of input values.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种不降低传送性能的通信控制装置，即使在通过线路传输的情况下，也不在多个输入模块中添加计数器，在过程控制系统中。 解决方案：在目的地通信控制设备中提供时间计数器。 此外，在目的地通信控制装置中设置用于临时存储输入数据的输入缓冲器和临时存储时间计数器的时间计数值的时间缓冲器。 同时允许这些缓冲区更新数据。 目的地通信控制装置具有用于发送单个时间值和多个输入值的装置。 源通信控制装置具有用于将单个时间值扩展成多个输入值的装置。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008299767A

公开(公告)日：2008-12-11

申请号：JP2007147692

申请日：2007-06-04

Applicant: Hitachi Information & Control Solutions Ltd ,  Hitachi Ltd ,  株式会社日立情報制御ソリューションズ ,  株式会社日立製作所

Inventor： OTANI TATSUYUKI ,  BANDO AKIRA ,  OGURA MAKOTO ,  SAKATA TERUAKI ,  KOBAYASHI EIJI ,  ONOZUKA AKIHIRO ,  KOBAYASHI MASAMITSU ,  FUNAKI SATORU ,  FURUTA YASUYUKI ,  ISHIKAWA MASAKAZU ,  SHIRAISHI MASAHIRO

IPC: G06F11/22 ,  G06F11/18

Abstract: PROBLEM TO BE SOLVED: To improve the entire failure detection rate by performing failure detection without depending on an output of a processing part and performing failure detection of a comparing part for performing the failure detection without limiting execution timing. SOLUTION: This diagnostic device is provided with the comparing part for detecting a failure of processing parts by comparing two pieces of output information output from duplicated two processing parts, a failure information injecting part for injecting pseudo failure information so that the comparing part may detect the processing parts have a failure into the comparing part, and a failure determination part for performing failure determination of the comparing part by using a detection result of the comparing part to which the pseudo failure information is injected. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过执行故障检测来提高整个故障检测率，而不依赖于处理部分的输出，并且在不限制执行定时的情况下执行用于执行故障检测的比较部分的故障检测。 解决方案：通过比较从复制的两个处理部分输出的两条输出信息，用于注入伪故障信息的故障信息注入部分，使得该诊断装置具有用于检测处理部分的故障的比较部分，使得比较部分 可以将处理部分检测到失败到比较部分，以及故障确定部分，用于通过使用注射了伪故障信息的比较部分的检测结果来执行比较部分的故障确定。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008059448A

公开(公告)日：2008-03-13

申请号：JP2006237710

申请日：2006-09-01

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： SAKATA TERUAKI ,  SHIMAMURA KOTARO ,  BANDO AKIRA ,  KOBAYASHI MASAMITSU ,  SHIRAISHI MASAHIRO ,  OGURA MAKOTO ,  KOBAYASHI EIJI ,  SEKI YUSUKE

IPC: G06F13/36

CPC classification number: G06F11/364

Abstract: PROBLEM TO BE SOLVED: To provide a bus system capable of guaranteeing the reliability of transfer data even though abnormality occurs in a master or a slave uninvolved in transfer during transferring data whose reliability should be guaranteed in the bus system in which a plurality of masters 1 and 2 and slaves 3 and 4 are connected to a bus 5.
SOLUTION: The bus system is provided with bus switches 31 to 34 and a switch control part 11. During priority (security) data transfer, a priority (security) data signal 71 is defined as "1", and bus switches 32 and 34 of the master 2 and the slave 4 uninvolved in the transfer are turned off, and while during normal data transfer, the priority (security) data signal 71 is defined as "0", and all of the bus switches 31 to 34 are turned on.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种能够保证传送数据的可靠性的总线系统，即使在传输中的主机或从机中的异常发生，在传输数据时，其可靠性应当在总线系统中保证，其中多个 主机1和2以及从机3和4连接到总线5.解决方案：总线系统设置有总线开关31至34和开关控制部分11.在优先级（安全性）数据传输期间，优先级 （安全性）数据信号71被定义为“1”，并且主机2的总线开关32和34以及从动装置4中不涉及传送的总线开关32和34被关断，而在正常的数据传输期间，优先级（安全性）数据信号71 被定义为“0”，并且所有总线开关31至34都被接通。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007067761A

公开(公告)日：2007-03-15

申请号：JP2005250495

申请日：2005-08-31

Applicant: Hitachi Information & Control Solutions Ltd ,  Hitachi Ltd ,  株式会社日立情報制御ソリューションズ ,  株式会社日立製作所

Inventor： ONOZUKA AKIHIRO ,  SHIRAISHI MASAHIRO ,  KOBAYASHI MASAMITSU ,  OGURA MAKOTO ,  UMEHARA TAKASHI ,  ISHIKAWA MASAKAZU ,  KOBAYASHI EIJI ,  FURUTA YASUYUKI ,  ENDO HIROMICHI ,  FUNAKI SATORU ,  BANDO AKIRA

IPC: H04L1/14 ,  H04L12/707 ,  H04L12/813 ,  H04L29/08

Abstract: PROBLEM TO BE SOLVED: To provide a communication control apparatus capable of reducing an oversight error rate and carrying out masquerade detection over security functions in a process control system. SOLUTION: A data receiver side applies echo-back transmission to data, a data transmission source collates the data and informs a result of the collation of the data receiver side. The communication control apparatus comprises: a master communication control apparatus; and a slave communication control apparatus connected to an output circuit, the master communication control apparatus transmits output data, the slave communication control apparatus transmits echo-back of the output data, and the master communication control apparatus collates the output data with the echo-back and permits an output to the slave communication control apparatus when they are coincident. The communication control apparatus comprises the master communication control apparatus and the slave communication control apparatus connected to an input circuit, the slave communication control apparatus transmits input data, the master communication control apparatus transmits echo-back of the input data, and the slave communication control apparatus collates the input data and the echo-back and permits an input to the master communication control apparatus when they are coincident. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够降低监视错误率并且在过程控制系统中对安全功能执行伪装检测的通信控制装置。 解决方案：数据接收机侧对数据应用回波传输，数据传输源对数据进行比较并通知数据接收机侧的核对结果。 通信控制装置包括：主通信控制装置; 以及连接到输出电路的从属通信控制装置，主通信控制装置发送输出数据，从属通信控制装置发送输出数据的回波，主通信控制装置将输出数据与回波 并且当从属通信控制装置重合时允许输出到从通信控制装置。 通信控制装置包括连接到输入电路的主通信控制装置和从通信控制装置，从通信控制装置发送输入数据，主通信控制装置发送输入数据的回波和从通信控制 装置对输入数据和回波进行整理，并且当它们重合时允许对主通信控制装置的输入。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007052689A

公开(公告)日：2007-03-01

申请号：JP2005238229

申请日：2005-08-19

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： KASAHARA TAKENORI ,  OGURA MAKOTO ,  KOBAYASHI MASAMITSU ,  ISHIKAWA MASAKAZU ,  BANDO AKIRA ,  ENDO HIROMICHI

IPC: G06F12/16

Abstract: PROBLEM TO BE SOLVED: To provide a control system with improved reliability by detecting even a failure of an address line before writing data into a wrong address.
SOLUTION: A system control circuit 120 transfers data to a memory 140, and writes the data to the assigned address of the memory 140 or reads the data from the assigned address of the memory 140. An error detecting circuit 134 of a memory control device 130 detects the error of the address assigned to the memory 140. A control circuit 136 allows the data transfer to the memory 140 when the assigned address is correct.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过在将数据写入错误的地址之前甚至检测地址线的故障来提供具有改进的可靠性的控制系统。 解决方案：系统控制电路120将数据传送到存储器140，并将数据写入存储器140的分配地址，或从存储器140的分配地址读取数据。存储器的错误检测电路134 控制装置130检测分配给存储器140的地址的错误。当分配的地址正确时，控制电路136允许数据传送到存储器140。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000259586A

公开(公告)日：2000-09-22

申请号：JP5972599

申请日：1999-03-08

Applicant: HITACHI LTD

Inventor： TAKEWA HIDEHITO ,  OGURA MAKOTO ,  MATSUDA KOJI ,  ISHIKURA HIDEJI ,  KUROSAWA KENICHI

IPC: G06F15/177

Abstract: PROBLEM TO BE SOLVED: To control the configuration of a system consisting of plural processors and also to shorten the control processing time of the system configuration by providing a management table to which the processors can have accesses with no control required for the configuration of a main memory. SOLUTION: A system LSI 108 includes a management table 126, and the processors 100-103 access the table 126 via the signal lines 104-107. The table 126 consists of a row, a configuration control area and a flag. The flag value of '0' shows that the configuration control processing is not executed yet, and the flag value of '1' shows that the constitution control processing is already executed or being executed. When a power supply is turned on, the processors 100-103 execute the constitution control programs stored in a rise memory 111. Thus, a system can carry out the parallel processes by means of the table 126 even when a main memory 112 undergoes no configuration control and is unusable since the table 126 is constructed in the LSI 108 and not in the memory 112.

公开(公告)号：JPH11194990A

公开(公告)日：1999-07-21

申请号：JP24398

申请日：1998-01-05

Applicant: HITACHI LTD

Inventor： YAMADA TSUTOMU ,  KUROSAWA KENICHI ,  OGURA MAKOTO ,  MASUI KOJI

IPC: G06F13/14 ,  G06F13/36

Abstract: PROBLEM TO BE SOLVED: To provide a bus bridge circuit which can be utilized without changing a correspondent device driver even when an arbitrary device and a bus bridge are integrated and changed to a bus bridge to be directly connected top processor buses. SOLUTION: This bus bridge circuit 1 with which first buses 10-30 are mutually connected to second buses 19-39 is provided with an address decode means 2 which outputs a select signal to an address range on the first buses 10-30 corresponding to a device T on the second buses 19-39, an area enable circuit 40 which instructs whether or not the bus bridge circuit 1 is to respond to the select signal for each device T on the second buses 19-39, an area enabler 3 which outputs a start signal for determining bridge operation based on the select signal and the area enable instruction, and a bridge sequence which executes master operation on the second buses 19-39 corresponding to the start signal.

公开(公告)号：JP2014073017A

公开(公告)日：2014-04-21

申请号：JP2012218346

申请日：2012-09-28

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： OIRI AKIRA ,  BANDO AKIRA ,  MORITA AKIHIRO ,  OGURA MAKOTO ,  HIGUCHI MIKIMASA

IPC: H02M1/00 ,  H02M7/12

Abstract: PROBLEM TO BE SOLVED: To provide a failure detection device and a failure detection method for a power conversion system capable of detecting an anomaly of a voltage detector and failure of an element while distinguishing them.SOLUTION: A failure detection device includes a forward voltage detector 21 for detecting a forward voltage across an anode and a cathode of a thyristor 11, a reverse voltage detector 31 for detecting a reverse voltage across the anode and the cathode of the thyristor 11, and a failure detection part 172 for executing failure detection processing which includes determination of element failure of the thyristor 11, to which the forward voltage detector 21 and the reverse voltage detector 31 are connected in parallel, failure of the forward voltage detector 11, and failure of the reverse voltage detector 31, based on a forward voltage detection signal inputted from the forward voltage detector 21 and a reverse voltage detection signal inputted from the reverse voltage detector 31.

Abstract translation: 要解决的问题：提供一种能够检测电压检测器的异常并且识别元件故障的电力变换系统的故障检测装置和故障检测方法。解决方案：故障检测装置包括正向电压检测器 21，用于检测跨越晶闸管11的阳极和阴极的正向电压;用于检测晶闸管11的阳极和阴极两端的反向电压的反向电压检测器31;以及用于执行故障检测处理的故障检测部172， 包括基于正向电压确定正向电压检测器21和反向电压检测器31并联连接的晶闸管11的元件故障，正向电压检测器11的故障和反向电压检测器31的故障 从正向电压检测器21输入的检测信号和从反向电压输入的反向电压检测信号 年龄检测器31。

公开(公告)号：JP2011257904A

公开(公告)日：2011-12-22

申请号：JP2010130745

申请日：2010-06-08

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： MATSUMOTO NORITAKE ,  YAMADA TSUTOMU ,  OHASHI AKIHIRO ,  OGURA MAKOTO

IPC: G06F9/455 ,  G05B19/05 ,  G06F9/48

CPC classification number: G06F9/3017 ,  G05B19/052 ,  G05B2219/13028 ,  G05B2219/15114

Abstract: PROBLEM TO BE SOLVED: To provide a new control apparatus for preventing a reduction in processing speed due to code conversion of a program when a sequence processing program having an instruction set of another processor is executed on its own processor.SOLUTION: A processor 2 reads data from a storage unit 3, performs a process described as a program, and notifies a conversion command unit 6 of a command to change a data acquisition method from the storage unit 3 in accordance with content of the data. The conversion command unit 6 changes an operation of a change unit 5 due to the notification from the processor 2. The change unit 5 is connected directly or indirectly via a conversion unit 4 to the storage unit 3, and changes a data reading method from the storage unit 3 in accordance with an indication from the conversion command unit 6. The conversion unit 4 converts the data read from the storage unit 3 to data that can be processed by the processor 2 in accordance with a conversion method described later.

Abstract translation: 要解决的问题：提供一种新的控制装置，用于当在其自己的处理器上执行具有另一处理器的指令集的序列处理程序时，防止由程序的代码转换引起的处理速度的降低。 解决方案：处理器2从存储单元3读取数据，执行被描述为程序的处理，并且根据存储单元3的内容向存储单元3通知转换命令单元6改变数据获取方法的命令 数据。 转换指令单元6改变由于来自处理器2的通知而导致的改变单元5的操作。改变单元5经由转换单元4直接或间接地连接到存储单元3，并将数据读取方法从 存储单元3根据来自转换命令单元6的指示。转换单元4根据稍后描述的转换方法将从存储单元3读取的数据转换成可由处理器2处理的数据。 版权所有（C）2012，JPO＆INPIT