公开(公告)号：HUE042292T2

公开(公告)日：2019-06-28

申请号：HUE12878862

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F9/54 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

公开(公告)号：AU2018209038A1

公开(公告)日：2019-06-13

申请号：AU2018209038

申请日：2018-01-03

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SAPORITO ANTHONY ,  PAPROTSKI VOLODYMYR ,  MITRAN MARCEL

IPC: G06F9/30

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

公开(公告)号：HUE040014T2

公开(公告)日：2019-02-28

申请号：HUE12878813

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F11/07 ,  G06F9/38 ,  G06F11/36

公开(公告)号：PL2834739T3

公开(公告)日：2018-12-31

申请号：PL12878813

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F11/07 ,  G06F9/38 ,  G06F11/36

公开(公告)号：SI2834739T1

公开(公告)日：2018-11-30

申请号：SI201231395

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F11/00 ,  G06F9/00

公开(公告)号：SI2825961T1

公开(公告)日：2018-03-30

申请号：SI201330861

申请日：2013-03-01

Applicant: IBM

Inventor： GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  STOODLEY KEVIN A

IPC: G06F11/00

公开(公告)号：DE112015000203T5

公开(公告)日：2016-09-01

申请号：DE112015000203

申请日：2015-02-23

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SCHMIDT DONALD WILLIAM ,  MITRAN MARCEL ,  GAINEY CHARLES JR

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: Bereitgestellt wird eine Verzögerungseinrichtung, in der eine Programmausführung verzögert werden kann, bis ein vordefiniertes Ereignis eintritt, z. B. bis ein Vergleich von Arbeitsspeicherpositionen eine wahre Bedingung ergibt, eine Zeitüberschreitung erreicht wird, eine Unterbrechung ausgesetzt wird oder eine andere Bedingung gegeben ist. Die Verzögerungseinrichtung beinhaltet einen oder mehrere „Compare and Delay”-Maschinenbefehle, mit denen eine Ausführung verzögert wird. Der eine oder die mehreren „Compare and Delay”-Befehle können einen 32-Bit-„Compare and Delay”-Befehl (CAD-Befehl) und einen 64-Bit-„Compare and Delay”-Befehl (CADG-Befehl) beinhalten.

公开(公告)号：AU2013233830B2

公开(公告)日：2016-06-23

申请号：AU2013233830

申请日：2013-03-01

Applicant: IBM

Inventor： FARRELL MARK S ,  GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  SLEGEL TIMOTHY J ,  SMITH BRIAN LEONARD ,  STOODLEY KEVIN A

IPC: G06F11/34

Abstract: Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

公开(公告)号：AU2013233831B2

公开(公告)日：2016-05-12

申请号：AU2013233831

申请日：2013-03-01

Applicant: IBM

Inventor： GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  STOODLEY KEVIN A

IPC: G06F11/34

Abstract: Embodiments of the invention relate to implementing run-time instrumentation directed sampling. An aspect of the invention includes a method for implementing run-time instrumentation directed sampling. The method includes fetching a run-time instrumentation next (RINEXT) instruction from an instruction stream. The instruction stream includes the RINEXT instruction followed by a next sequential instruction (NSI) in program order. The method further includes executing the RINEXT instruction by a processor. The executing includes determining whether a current run-time instrumentation state enables setting a sample point for reporting run-time instrumentation information during program execution. Based on the current run-time instrumentation state enabling setting the sample point, the NSI is a sample instruction for causing a run-time instrumentation event. Based on executing the NSI sample instruction, the run-time instrumentation event causes recording of run-time instrumentation information into a run-time instrumentation program buffer as a reporting group.

公开(公告)号：AU2012360180B2

公开(公告)日：2016-04-07

申请号：AU2012360180

申请日：2012-11-13

Applicant: IBM

Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  MITRAN MARCEL ,  COPELAND REID

IPC: G06F9/30

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.