公开(公告)号：US11145745B2

公开(公告)日：2021-10-12

申请号：US16514292

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Christian Kampen ,  Andreas Meiser

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/06

Abstract: A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.

公开(公告)号：US10964808B2

公开(公告)日：2021-03-30

申请号：US16144880

申请日：2018-09-27

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Romain Esteve ,  Roland Rupp

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/417 ,  H01L29/04 ,  H01L29/872

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.

公开(公告)号：US10734484B2

公开(公告)日：2020-08-04

申请号：US16358929

申请日：2019-03-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Roland Rupp ,  Oana Julia Spulber

IPC: H01L31/0256 ,  H01L21/336 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/225 ,  H01L29/10

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.

公开(公告)号：US20200176568A1

公开(公告)日：2020-06-04

申请号：US16700475

申请日：2019-12-02

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder ,  Roland Rupp

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a silicon carbide semiconductor body including a source region of a first conductivity type, a body region of a second conductivity type, shielding regions of the second conductivity type and compensation regions of the second conductivity type. Trench structures extend from a first surface into the silicon carbide semiconductor body along a vertical direction. Each of the trench structures includes an auxiliary electrode at a bottom of the trench structure and a gate electrode between the auxiliary electrode and the first surface. The auxiliary electrode is electrically insulated from the gate electrode. The auxiliary electrode of each of the trench structures is adjoined by at least one of the shielding regions at the bottom of the trench structure. Each of the shielding regions is adjoined by at least one of the compensation regions at the bottom of the shielding region.

公开(公告)号：US20200152743A1

公开(公告)日：2020-05-14

申请号：US16745015

申请日：2020-01-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder ,  Roland Rupp

IPC: H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40

Abstract: A method of manufacturing a silicon carbide device includes: forming a trench in a process surface of a silicon carbide substrate that has a body layer forming second pn junctions with a drift layer structure, wherein the body layer is between the process surface and the drift layer structure and wherein the trench exposes the drift layer structure; implanting dopants through a bottom of the trench to form a shielding region that forms a first pn junction with the drift layer structure; forming dielectric spacers on sidewalls of the trench; and forming a buried portion of an auxiliary electrode in a bottom section of the trench, the buried portion adjoining the shielding region.

公开(公告)号：US20190189742A1

公开(公告)日：2019-06-20

申请号：US16220693

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Christian Kampen

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0696 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/7835

Abstract: The disclosure relates to a semiconductor device including a first planar field effect transistor cell and a second planar field effect transistor cell. The first planar field effect transistor cell and the second planar field effect transistor cell are electrically connected in parallel and each include a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. A gate electrode of the first field effect transistor cell is electrically connected to a source terminal, and a gate electrode of the second field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal.

公开(公告)号：US20180108675A1

公开(公告)日：2018-04-19

申请号：US15785627

申请日：2017-10-17

Applicant: Infineon Technologies AG

Inventor： Sebastian Schmidt ,  Donald Dibra ,  Oliver Hellmund ,  Peter Irsigler ,  Andreas Meiser ,  Hans-Joachim Schulze ,  Martina Seider-Schmidt ,  Robert Wiesner

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L21/84

Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

公开(公告)号：US20180006639A1

公开(公告)日：2018-01-04

申请号：US15639834

申请日：2017-06-30

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Andreas Meiser

IPC: H03K17/08 ,  H01L23/00

CPC classification number: H03K17/08 ,  H01L24/05 ,  H01L24/45 ,  H03K17/0822

Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.

公开(公告)号：US09825148B2

公开(公告)日：2017-11-21

申请号：US15160525

申请日：2016-05-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/40 ,  H01L21/76 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

公开(公告)号：US20170263719A1

公开(公告)日：2017-09-14

申请号：US15603623

申请日：2017-05-24

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Markus Zundel ,  Anton Mauder ,  Andreas Meiser ,  Franz Hirler ,  Hans Weber

IPC: H01L29/40 ,  H01L21/308 ,  H01L21/265 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L21/225

CPC classification number: H01L29/407 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/225 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/3081 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66696 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor structure is provided, which may include: forming a p-doped region adjacent to an n-doped region in a substrate; carrying out an anodic oxidation to form an oxide layer on a surface of the substrate, wherein the oxide layer in a first portion of the surface extending along the n-doped region has a greater thickness than the oxide layer in a second portion of the surface extending along the p-doped region.