公开(公告)号：US11217658B2

公开(公告)日：2022-01-04

申请号：US16423535

申请日：2019-05-28

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Grzegorz Kozlowski ,  Till Schloesser

IPC: H01L49/02 ,  H01L21/761 ,  H01L21/762

Abstract: The disclosure relates to a semiconductor device, including a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, the second conductivity type being different than the first conductivity type. The semiconductor device also includes an isolation structure electrically isolating a first region of the semiconductor layer from a second region of the semiconductor layer. A shallow trench isolation structure vertically extends from a surface of the semiconductor layer into the first region of the semiconductor layer. An electrical resistor is formed on the shallow trench isolation structure.

公开(公告)号：US11177354B2

公开(公告)日：2021-11-16

申请号：US16745015

申请日：2020-01-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder ,  Roland Rupp

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04 ,  H01L29/739

Abstract: A method of manufacturing a silicon carbide device includes: forming a trench in a process surface of a silicon carbide substrate that has a body layer forming second pn junctions with a drift layer structure, wherein the body layer is between the process surface and the drift layer structure and wherein the trench exposes the drift layer structure; implanting dopants through a bottom of the trench to form a shielding region that forms a first pn junction with the drift layer structure; forming dielectric spacers on sidewalls of the trench; and forming a buried portion of an auxiliary electrode in a bottom section of the trench, the buried portion adjoining the shielding region.

公开(公告)号：US10985248B2

公开(公告)日：2021-04-20

申请号：US16354973

申请日：2019-03-15

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Romain Esteve ,  Anton Mauder ,  Andreas Meiser ,  Bernd Zippelius

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.

公开(公告)号：US10586851B2

公开(公告)日：2020-03-10

申请号：US15934518

申请日：2018-03-23

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder ,  Roland Rupp

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/04 ,  H01L29/417 ,  H01L29/40 ,  H01L21/02

Abstract: A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body. The trench structure includes an auxiliary electrode at a bottom of the trench structure and a gate electrode arranged between the auxiliary electrode and the first surface. A shielding region adjoins the auxiliary electrode at the bottom of the trench structure and forms a first pn junction with a drift structure. A corresponding method of manufacturing the semiconductor device is also described.

公开(公告)号：US10453915B2

公开(公告)日：2019-10-22

申请号：US15941637

申请日：2018-03-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Karl-Heinz Bach ,  Christian Kampen ,  Dietmar Kotz ,  Andrew Christopher Graeme Wood ,  Markus Zundel

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265

Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.

公开(公告)号：US20190296110A1

公开(公告)日：2019-09-26

申请号：US16358929

申请日：2019-03-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Roland Rupp ,  Oana Julia Spulber

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/225 ,  H01L29/423

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.

公开(公告)号：US10355087B2

公开(公告)日：2019-07-16

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/265

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

公开(公告)号：US20190189743A1

公开(公告)日：2019-06-20

申请号：US16220592

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Grzegorz Kozlowski

IPC: H01L29/08 ,  H01L29/735 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/735 ,  H01L29/7835

Abstract: The disclosure relates to a planar field effect transistor. The planar field effect transistor includes a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. The planar field effect transistor also includes a first electrode part and a second electrode part laterally spaced apart from the first electrode part. The first electrode part is arranged as a gate electrode above the channel region. The second electrode part is arranged above the drain extension region and is electrically isolated from the first electrode part.

公开(公告)号：US10246325B2

公开(公告)日：2019-04-02

申请号：US14832001

申请日：2015-08-21

Applicant: Infineon Technologies AG

Inventor： Stefan Kolb ,  Andreas Meiser ,  Till Schloesser ,  Wolfgang Werner

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/00

Abstract: A method for producing a MEMS device comprises forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer and a third monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers. A semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers. After forming the semiconductor layer stack, at least a portion of each of the first and third monocrystalline semiconductor layers is concurrently etched.

公开(公告)号：US20180277637A1

公开(公告)日：2018-09-27

申请号：US15934518

申请日：2018-03-23

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Caspar Leendertz ,  Anton Mauder ,  Roland Rupp

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02

Abstract: A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body. The trench structure includes an auxiliary electrode at a bottom of the trench structure and a gate electrode arranged between the auxiliary electrode and the first surface. A shielding region adjoins the auxiliary electrode at the bottom of the trench structure and forms a first pn junction with a drift structure. A corresponding method of manufacturing the semiconductor device is also described.