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    PACKAGE STRUCTURES INCLUDING DISCRETE ANTENNAS ASSEMBLED ON A DEVICE
    91.
    发明申请
    PACKAGE STRUCTURES INCLUDING DISCRETE ANTENNAS ASSEMBLED ON A DEVICE 审中-公开
    包装结构包括在装置上组装的离散天线

    公开(公告)号：WO2014099032A1

    公开(公告)日：2014-06-26

    申请号：PCT/US2013/048671

    申请日：2013-06-28

    Applicant: INTEL CORPORATION ,  KAMGAING, Telesphor ,  RAO, Valluri R. ,  DEGANI, Ofir

    Inventor： KAMGAING, Telesphor ,  RAO, Valluri R. ,  DEGANI, Ofir

    IPC: H01Q1/38 ,  H01Q1/24

    CPC classification number: H01Q9/045 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01P11/00 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/526 ,  H01Q21/0006 ,  Y10T29/49018

    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device.

    Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括形成包括设置在设备的背侧的分立天线的封装结构，其中分立天线包括天线基板，通过天线基板垂直设置的通过天线基板。 垂直设置在器件内的穿通器件衬底通孔经由天线衬底与封装衬底耦合，并且封装衬底与器件的有源侧耦合。

    INTEGRATED MILLIMETER WAVE ANTENNA ESD PROTECTION
    93.
    发明公开
    INTEGRATED MILLIMETER WAVE ANTENNA ESD PROTECTION 审中-公开

    公开(公告)号：EP4456320A1

    公开(公告)日：2024-10-30

    申请号：EP23216209.9

    申请日：2023-12-13

    Applicant: INTEL Corporation

    Inventor： GOSSNER, Harald ,  WAGNER, Thomas ,  WAIDHAS, Bernd ,  SEIDEMANN, Georg ,  YANG, Tae Young ,  KAMGAING, Telesphor

    IPC: H01Q1/22 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q9/04 ,  H01L23/60 ,  H01L23/64 ,  H01L23/66

    Abstract: An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

    LAYER TRANSFER ON NON-SEMICONDUCTOR SUPPORT STRUCTURES
    95.
    发明公开
    LAYER TRANSFER ON NON-SEMICONDUCTOR SUPPORT STRUCTURES 审中-公开

    公开(公告)号：EP4105981A1

    公开(公告)日：2022-12-21

    申请号：EP22174054.1

    申请日：2022-05-18

    Applicant: INTEL Corporation

    Inventor： SHARMA, Abhishek Anil ,  GOMES, Wilfred ,  KAMGAING, Telesphor

    IPC: H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L21/20

    Abstract: Embodiments of the present disclosure relate to methods of fabricating IC devices using layer transfer and resulting IC devices, assemblies, and systems. An example method includes fabricating a device layer over a semiconductor support structure, the device layer comprising a plurality of frontend devices; attaching the semiconductor support structure with the device layer to a carrier substrate so that the device layer is closer to the carrier substrate than the semiconductor support structure; removing at least a portion of the semiconductor support structure to expose the device layer; and bonding a support structure of a non-semiconductor material having a dielectric constant that is smaller than a dielectric constant of silicon (e.g., a glass wafer) to the exposed frontend layer. The carrier substrate may then be removed.

    SEMICONDUCTOR PACKAGES WITH ANTENNAS
    96.
    发明公开
    SEMICONDUCTOR PACKAGES WITH ANTENNAS 审中-公开

    公开(公告)号：EP3731270A1

    公开(公告)日：2020-10-28

    申请号：EP20175885.1

    申请日：2016-07-01

    Applicant: INTEL Corporation

    Inventor： KAMGAING, Telesphor ,  ELSHERBINI, Adel A. ,  OSTER, Sasha N.

    IPC: H01L23/66 ,  H01L23/498 ,  H01Q1/22 ,  H01Q19/00 ,  H01Q9/04

    Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

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