公开(公告)号：US10719355B2

公开(公告)日：2020-07-21

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

公开(公告)号：US10579414B2

公开(公告)日：2020-03-03

申请号：US15477064

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan ,  Daniel Deng ,  Jared W. Stark ,  Ronak Singhal ,  Hong Wang

IPC: G06F9/38 ,  G06F9/46

Abstract: Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

公开(公告)号：US20200004542A1

公开(公告)日：2020-01-02

申请号：US16021838

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Zeev Sperber ,  Sumeet Bandishte ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Kamil Garifullin ,  Sreenivas Subramoney ,  Adi Yoaz ,  Hong Wang

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

公开(公告)号：US20190205143A1

公开(公告)日：2019-07-04

申请号：US15857863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Niranjan Soundararajan ,  Sreenivas Subramoney

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

CPC classification number: G06F9/3848 ,  G06F9/3005 ,  G06F9/321 ,  G06F9/3806 ,  G06F9/3844

Abstract: In one embodiment, a branch prediction circuit includes: a first bimodal predictor having a first plurality of entries each to store first prediction information for a corresponding branch instruction; a global predictor having a plurality of global entries each to store global prediction information for a corresponding branch instruction; a second bimodal predictor having a second plurality of entries each to store second prediction information for a corresponding branch instruction; a monitoring table having a plurality of monitoring entries each to store a counter value based on the second prediction information for a corresponding branch instruction; and a control circuit to allocate a global entry within the global predictor based at least in part on the counter value of a monitoring entry of the monitoring table for a corresponding branch instruction. Other embodiments are described and claimed.

公开(公告)号：US20180314903A1

公开(公告)日：2018-11-01

申请号：US15582945

申请日：2017-05-01

Applicant: INTEL CORPORATION

Inventor： Gurpreet S. Kalsi ,  Om J. Omer ,  Biji George ,  Gopi Neela ,  Dipan Kumar Mandal ,  Sreenivas Subramoney

IPC: G06K9/00 ,  G06K9/46

CPC classification number: G06K9/00973 ,  G06K9/4604 ,  G06K9/4647

Abstract: One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.

公开(公告)号：US20180285286A1

公开(公告)日：2018-10-04

申请号：US15477069

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sriseshan Srikanth ,  Lavanya Subramanian ,  Sreenivas Subramoney

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/38 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F13/161 ,  G06F9/3838 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4059 ,  G11C7/1072 ,  G11C7/22

Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.

公开(公告)号：US20180173533A1

公开(公告)日：2018-06-21

申请号：US15383832

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan

IPC: G06F9/38

Abstract: A processor may include a baseline branch predictor and an empirical branch bias override circuit. The baseline branch predictor may receive a branch instruction associated with a given address identifier, and generate, based on a global branch history, an initial prediction of a branch direction for the instruction. The empirical branch bias override circuit may determine, dependent on a direction of an observed branch direction bias in executed branch instruction instances associated with the address identifier, whether the initial prediction should be overridden, may determine, in response to determining that the initial prediction should be overridden, a final prediction that matches the observed branch direction bias, or may determine, in response determining that the initial prediction should not be overridden, a final prediction that matches the initial prediction. The predictor may update an entry in the global branch history reflecting the resolved branch direction for the instruction following its execution.

公开(公告)号：US20180121353A1

公开(公告)日：2018-05-03

申请号：US15335924

申请日：2016-10-27

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Sreenivas Subramoney ,  Leon Polishuk

IPC: G06F12/0804 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/12 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Systems, methods, and processors to reduce redundant writes to memory. An embodiment of a system includes: a plurality of processors; a memory coupled to one of more of the plurality of processors; a cache coupled to the memory such that a dirty cache line evicted from the cache is written to the memory; and a redundant write detection circuitry coupled to the cache, wherein the redundant write detection circuitry to control write access to the cache based on a redundancy check of data to be written to the cache. The system may include a first predictor circuitry to deactivate the redundant write detection circuitry responsive to a determination that power consumed by the redundancy check is greater than the power it saves, or a second predictor circuitry to deactivate the redundant write detection circuitry when memory bandwidth saved from performing the redundancy check is not being utilized by memory reads.

公开(公告)号：US20180088944A1

公开(公告)日：2018-03-29

申请号：US15275066

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Anant Nori

IPC: G06F9/30 ,  G06F12/0862 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/3009 ,  G06F9/30047 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

公开(公告)号：US12140696B2

公开(公告)日：2024-11-12

申请号：US17375017

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Chulong Chen ,  Wenling Margaret Huang ,  Saiveena Kesaraju ,  Ivan Simões Gaspar ,  Pradyumna S. Singh ,  Biji George ,  Dipan Kumar Mandal ,  Om Ji Omer ,  Sreenivas Subramoney ,  Yuval Amizur ,  Leor Banin ,  Hao Chen ,  Nir Dvorecki ,  Shengbo Xu

IPC: G01S7/41 ,  G01S7/40 ,  G01S13/58 ,  G01S13/89 ,  H01Q15/02 ,  H01Q21/06

Abstract: According to various embodiments, a radar device is described comprising a processor configured to generate a scene comprising an object based on a plurality of receive wireless signals, generate a ground truth object parameter of the object and generate a dataset representative of the scene and a radar detector configured to determine an object parameter of the object using a machine learning algorithm and the dataset, determine an error value of the machine learning algorithm using a cost function, the object parameter, and the ground truth object parameter and adjust the machine learning algorithm values to reduce the error value.