公开(公告)号：US20250110813A1

公开(公告)日：2025-04-03

申请号：US18375069

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ashish Gupta ,  William Bainbridge

IPC: G06F9/54

Abstract: Techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. In various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (CMB). The target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. Communications via the CMB enable the target agent to determine, during a runtime of the network, whether a given initiator agent has been allocated an excessive number of credits, or an insufficient number of credits. In another embodiments, the target agent changes the distribution of credits to the initiator agents by allocating credits via the CMB.

公开(公告)号：US12197374B2

公开(公告)日：2025-01-14

申请号：US17359321

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Nayan Amrutlal Suthar ,  David M. Puffer ,  Ashok Jagannathan

IPC: G06F13/42 ,  G06F12/0815 ,  G06T1/20

Abstract: A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.

公开(公告)号：US20230114164A1

公开(公告)日：2023-04-13

申请号：US17551681

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Aravindh Anantaraman ,  Lakshminarayana Pappu ,  Dongsheng Bi ,  Guadalupe J. Garcia ,  Altug Koker ,  Joydeep Ray ,  Rahul Joshi ,  Shrikul Atulkumar Joshi ,  Mahak Gupta

IPC: G06F12/0871 ,  G06F12/0891 ,  G06F13/16 ,  G06F13/28 ,  G06F15/78

Abstract: In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

公开(公告)号：US20190114243A1

公开(公告)日：2019-04-18

申请号：US16218078

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Umberto Santoni ,  Rahul Pal ,  Philip Abraham ,  Mahesh Mamidipaka ,  C. Santhosh

IPC: G06F11/273 ,  G06F11/16

CPC classification number: G06F11/273 ,  G06F11/1004 ,  G06F11/1616 ,  G06F11/1629 ,  G06F11/1633 ,  G06F11/1641 ,  G06F11/1666

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

公开(公告)号：US20180349144A1

公开(公告)日：2018-12-06

申请号：US15614757

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ragavendra Natarajan ,  Niranjan K. Soundararajan ,  Sreenivas Subramoney ,  Daniel Deng ,  Jared Warner Stark, IV ,  Hong Wang ,  Ronak Singhal

IPC: G06F9/38

Abstract: In one embodiment, a processor comprises a branch predictor to generate, in association with a program loop, a frozen history vector comprising a snapshot of a branch history vector; track a current iteration of the program loop; and provide a prediction for a branch instruction associated with the program loop, the prediction based on the frozen history vector and the current iteration of the program loop.

公开(公告)号：US20180285115A1

公开(公告)日：2018-10-04

申请号：US15477064

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan ,  Daniel Deng ,  Jared W. Stark ,  Ronak Singhal ,  Hong Wang

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/46 ,  G06F9/3848

Abstract: Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

公开(公告)号：US12229069B2

公开(公告)日：2025-02-18

申请号：US17083200

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

IPC: G06F13/40 ,  G06F13/42

Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

公开(公告)号：US20210200678A1

公开(公告)日：2021-07-01

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/0815 ,  G06F12/0893 ,  G06F11/10

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US10579414B2

公开(公告)日：2020-03-03

申请号：US15477064

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Niranjan K. Soundararajan ,  Saurabh Gupta ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan ,  Daniel Deng ,  Jared W. Stark ,  Ronak Singhal ,  Hong Wang

IPC: G06F9/38 ,  G06F9/46

Abstract: Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

公开(公告)号：US10514990B2

公开(公告)日：2019-12-24

申请号：US15823313

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

IPC: G06F11/20 ,  G06F11/18 ,  G06F11/14 ,  G06F9/38

Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.