公开(公告)号：US09469523B2

公开(公告)日：2016-10-18

申请号：US14694908

申请日：2015-04-23

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0006 ,  B81B7/007 ,  B81B2207/096 ,  B81C1/00301

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

公开(公告)号：US09279865B2

公开(公告)日：2016-03-08

申请号：US13467175

申请日：2012-05-09

Applicant: Lianjun Liu ,  Phillip Mather

Inventor： Lianjun Liu ,  Phillip Mather

IPC: G01R35/00 ,  G01R33/09 ,  G01R33/00 ,  G01R33/02

CPC classification number: G01R33/09 ,  G01R33/0035 ,  G01R33/0206 ,  G01R33/093 ,  G01R35/00 ,  G01R35/005

Abstract: A structure and method are provided for self-test of a Z axis sensor. Two self-test current lines are symmetrically positioned adjacent, but equidistant from, each sense element. The vertical component of the magnetic field created from a current in the self-test lines is additive in a flux guide positioned adjacent, and orthogonal to, the sense element; however, the components of the magnetic fields in the plane of the sense element created by each of the two self-test current line pairs cancel one another at the sense element center, resulting in only the Z axis magnetic field being sensed during the self-test.

Abstract translation: 提供了一种用于Z轴传感器自检的结构和方法。 两条自测电流线对称地定位在与每个感测元件相邻但等距离的位置。 由自检线中的电流产生的磁场的垂直分量在与感测元件相邻并正交的定向磁通导向器中是相加的; 然而，由两个自检电流线对中的每一个产生的感测元件的平面中的磁场的分量在感测元件中心彼此抵消，导致在自适应期间仅感测到Z轴磁场， 测试。

公开(公告)号：US09073746B2

公开(公告)日：2015-07-07

申请号：US14005185

申请日：2012-02-23

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: B81B3/00 ,  B81B1/00 ,  G01L9/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00158 ,  B81C1/00238 ,  B81C2203/0154 ,  B81C2203/0792 ,  G01L9/0042 ,  G01L9/0054

Abstract: A Micro Electromechanical System (MEMS) pressure sensor may include a first substrate provided with a sensitive diaphragm of a piezoresistive pressure sensing unit, an electrical connecting diffusion layer and a first bonding layer on a surface of the first substrate; and a second substrate provided with an inter-conductor dielectric layer, a conductor connecting layer in the inter-conductor dielectric layer and/or a second bonding layer on a surface of the second substrate. The second substrate may be arranged opposite to the first substrate, and the second substrate may be fixedly coupled to the first substrate via the first bonding layer and the second bonding layer; the pattern of the first bonding layer is corresponding to the pattern of the second bonding layer, and both the first bonding layer and the second bonding layer may be formed of a conductive material.

Abstract translation: 微机电系统（MEMS）压力传感器可以包括在第一基板的表面上设置有压阻压力感测单元的敏感隔膜，电连接扩散层和第一接合层的第一基板; 以及设置有导体间介电层的第二基板，导体间电介质层中的导体连接层和/或第二基板的表面上的第二接合层。 第二基板可以布置成与第一基板相对，并且第二基板可以经由第一接合层和第二接合层固定地耦合到第一基板; 第一接合层的图案对应于第二接合层的图案，并且第一接合层和第二接合层都可以由导电材料形成。

公开(公告)号：US09061885B2

公开(公告)日：2015-06-23

申请号：US14018091

申请日：2013-09-04

Applicant: Lisa H. Karlin ,  Lianjun Liu ,  Alex P. Pamatat ,  Paul M. Winebarger

Inventor： Lisa H. Karlin ,  Lianjun Liu ,  Alex P. Pamatat ,  Paul M. Winebarger

IPC: H01L33/48 ,  H01L33/62 ,  B81B3/00 ,  B81B7/00 ,  H01L21/50 ,  H01L21/78 ,  H01L23/04 ,  H01L33/54 ,  H01L23/00

CPC classification number: B81B3/0018 ,  B81B7/007 ,  H01L21/50 ,  H01L21/78 ,  H01L23/04 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L24/03 ,  H01L24/26 ,  H01L24/83 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/27

Abstract: A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).

Abstract translation: 晶片结构（88）包括器件晶片（20）和盖晶片（60）。 器件晶片（20）上的半导体管芯（22）各自包括微电子器件（26）和端子元件（28,30）。 阻挡层（36,52）位于器件晶片（20）的非活性区域（32,50）中。 盖晶片（60）耦合到器件晶片（20）并覆盖半导体管芯（22）。 去除盖晶片（60）的部分（72）以露出端子元件（28,30）。 障碍物（36,52）可以比元件（28,30）更高，并且用于在部分（72）被移除时防止部分（72）接触端子元件（28,30）。 晶片结构（88）被单个化以形成多个半导体器件（89），每个器件（89）包括由盖晶片（60）的一部分覆盖的微电子器件（26）和从其暴露的端子元件（28,30） 盖晶片（60）。

公开(公告)号：US09041213B2

公开(公告)日：2015-05-26

申请号：US13828810

申请日：2013-03-14

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0006 ,  B81B7/007 ,  B81B2207/096 ,  B81C1/00301

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

Abstract translation: 提供了用于制造微机电系统（“MEMS”）器件的方法，MEMS器件也是如此。 在一个实施例中，MEMS器件制造方法包括形成延伸到衬底晶片中的至少一个通孔开口，在衬底晶片上沉积导电材料体并进入通孔开口以产生通孔，将衬底晶片接合到 换能器晶片具有导电换能器层，并且在通孔和导电换能器层之间形成电连接。 衬底晶片被薄化以通过衬底晶片的底表面露出通孔，并且在衬底晶片的底表面上产生电气耦合到通孔的背面导体。

公开(公告)号：US09035671B2

公开(公告)日：2015-05-19

申请号：US13529065

申请日：2012-06-21

Applicant: Lianjun Liu ,  Phillip Mather

Inventor： Lianjun Liu ,  Phillip Mather

IPC: G01R1/00 ,  G01R35/00 ,  G01R33/00 ,  G01R33/09

CPC classification number: G01R1/07307 ,  G01R33/0035 ,  G01R33/09 ,  G01R35/00

Abstract: A probe card and method are provided for testing magnetic sensors at the wafer level. The probe card has one or more probe tips having a first pair of solenoid coils in parallel configuration on first opposed sides of each probe tip to supply a magnetic field in a first (X) direction, a second pair of solenoid coils in parallel configuration on second opposed sides of each probe tip to supply a magnetic field in a second (Y) direction orthogonal to the first direction, and an optional third solenoid coil enclosing or inscribing the first and second pair to supply a magnetic field in a third direction (Z) orthogonal to both the first and second directions. The first pair, second pair, and third coil are each symmetrical with a point on the probe tip array, the point being aligned with and positioned close to a magnetic sensor during test.

Abstract translation: 提供探针卡和方法来测试晶片级的磁性传感器。 探针卡具有一个或多个探针尖端，其具有在每个探针尖端的第一相对侧上并联配置的第一对螺线管线圈，以在第一（X）方向上提供磁场，第二对螺线管线圈以 每个探针尖端的第二相对侧在与第一方向正交的第二（Y）方向上提供磁场，以及可选的第三电磁线圈，其包围或刻写第一和第二对以在第三方向（Z ）与第一和第二方向正交。 第一对，第二对和第三线圈各自与探针尖端阵列上的点对称，在测试期间该点与磁性传感器对准并靠近磁性传感器。

公开(公告)号：US09000760B2

公开(公告)日：2015-04-07

申请号：US13406149

申请日：2012-02-27

Applicant: Lianjun Liu ,  Phillip Mather

Inventor： Lianjun Liu ,  Phillip Mather

IPC: G01R33/02 ,  G01R33/00 ,  G01R33/09

CPC classification number: G01R35/00 ,  G01R33/0011 ,  G01R33/093

Abstract: A method and apparatus eliminate magnetic domain walls in a flux guide by applying, either simultaneously or sequentially, a current pulse along serially positioned reset lines to create a magnetic field along the flux guide, thereby removing the magnetic domain walls. By applying the current pulses in parallel and stepping through pairs of shorter reset lines segments via switches, less voltage is required.

Abstract translation: 一种方法和装置通过同时或顺序地施加沿着串行位置的复位线的电流脉冲来消除磁通引导件中的磁畴壁，以沿着磁通导向器产生磁场，从而去除磁畴壁。 通过并联施加电流脉冲并通过开关逐步穿过较短的复位线段，需要更少的电压。

公开(公告)号：US08921952B2

公开(公告)日：2014-12-30

申请号：US13753034

申请日：2013-01-29

Applicant: Chad S Dawson ,  Dubravka Bilic ,  Lianjun Liu ,  Andrew C McNeil

Inventor： Chad S Dawson ,  Dubravka Bilic ,  Lianjun Liu ,  Andrew C McNeil

IPC: H01L29/84 ,  H04R23/00 ,  H01L21/00 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0018 ,  B81B3/0072 ,  B81B2203/0127 ,  B81C1/00015

Abstract: Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation.

Abstract translation: 提供了制造抗电微机电（MEMS）器件的方法，以及根据这些方法制造的MEMS器件。 在一个实施例中，该方法包括在衬底上形成牺牲体，在衬底上产生多层膜结构，以及去除牺牲体的至少一部分以在多层膜结构内形成内腔。 多层膜结构通过首先在牺牲体上方和周围形成基膜层使得基膜层具有非平面的上表面来制造。 然后去除预定厚度的基膜层，以使基膜层具有平坦的上表面。 在基膜层的平面上表面上形成盖膜层。 盖膜层由具有基本上平行的晶粒取向的材料构成。

公开(公告)号：US20140264909A1

公开(公告)日：2014-09-18

申请号：US13828810

申请日：2013-03-14

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0006 ,  B81B7/007 ,  B81B2207/096 ,  B81C1/00301

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

Abstract translation: 提供了用于制造微机电系统（“MEMS”）器件的方法，MEMS器件也是如此。 在一个实施例中，MEMS器件制造方法包括形成延伸到衬底晶片中的至少一个通孔开口，在衬底晶片上沉积导电材料体并进入通孔开口以产生通孔，将衬底晶片接合到 换能器晶片具有导电换能器层，并且在通孔和导电换能器层之间形成电连接。 衬底晶片被薄化以通过衬底晶片的底表面露出通孔，并且在衬底晶片的底表面上产生电气耦合到通孔的背面导体。

公开(公告)号：US20140239423A1

公开(公告)日：2014-08-28

申请号：US13781391

申请日：2013-02-28

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00793 ,  B81B3/0075 ,  B81B7/007 ,  B81B2207/096

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided. In one embodiment, the MEMS device fabrication method forming a via opening extending through a sacrificial layer and into a substrate over which the sacrificial layer has been formed. A body of electrically-conductive material is deposited over the sacrificial layer and into the via opening to produce an unpatterned transducer layer and a filled via in ohmic contact with the unpatterned transducer layer. The unpatterned transducer layer is then patterned to define, at least in part, a primary transducer structure. At least a portion of the sacrificial layer is removed to release at least one movable component of the primary transducer structure. A backside conductor, such as a bond pad, is then produced over a bottom surface of the substrate and electrically coupled to the filled via.

Abstract translation: 提供了用于制造微机电系统（“MEMS”）装置的方法。 在一个实施例中，MEMS器件制造方法形成延伸穿过牺牲层并穿过其中形成有牺牲层的衬底的通孔。 导电材料体沉积在牺牲层上并进入通孔开口，以产生未图案化的换能器层和与未图案化的换能器层欧姆接触的填充通孔。 然后将未图案化的换能器层图案化以至少部分地限定主换能器结构。 去除牺牲层的至少一部分以释放主换能器结构的至少一个可移动部件。 然后在衬底的底表面上产生背面导体，例如接合焊盘，并电耦合到填充的通孔。