公开(公告)号：JPH0779410A

公开(公告)日：1995-03-20

申请号：JP24630993

申请日：1993-09-06

Applicant: SONY CORP

Inventor： KATAYAMA HIROSHI ,  SOMEYA IKUO

IPC: H04N5/93

Abstract: PURPOSE:To obtain a waveform equalization device for a video signal in which equalization is implemented immediately after special reproduction is released. CONSTITUTION:A CPU 19 compares a time T1 when an iteration flag detected by an iteration flag detection circuit 16 is at a high level with a maximum required time T2 for special reproduction in a video signal reproduction system 1. As a result, in the case of T1 T2, the CPU 19 judges the operation to be other than the special reproduction, a new equalization filter coefficient is obtained based on the transmission characteristic of a transmission line 3 under the control of the CPU 19 and the equalization filter coefficient is set to an equalization device 18.

公开(公告)号：JPH0759120A

公开(公告)日：1995-03-03

申请号：JP20164493

申请日：1993-08-13

Applicant: SONY CORP

Inventor： OURA KOICHI ,  KAWAMURA YASUHIRO ,  ISOBE TOSHINOBU ,  SOMEYA IKUO ,  TSURUMOTO TAKASHI

IPC: H04N15/00

Abstract: PURPOSE:To devise the display device such that the luminance or the color temperature of a video image sensed actually by human eyes is seen the same when the video image is the same as a video image displayed on the display device regardless of the stereoscopic video image display device with/without an optical device. CONSTITUTION:In the stereoscopic video image display device which has a video signal processing circuit 32 receiving selectively a usual video signal or a stereoscopic video signal and a display device 33 receiving selectively a usual video signal or a stereoscopic video signal from the video signal processing circuit 32 and displaying selectively a usual video image or a stereoscopic video image and in which stereoscopic vision is attained by viewing a stereoscopic video image displayed on the display device 33 through an optical device 9, the video signal processing circuit 32 is provided with video quality changeover means 44, 45 selecting the luminance or the color temperature depending whether the usual video signal or the stereoscopic video signal is received.

公开(公告)号：JPH0738517A

公开(公告)日：1995-02-07

申请号：JP20271193

申请日：1993-07-22

Applicant: SONY CORP

Inventor： SHIBATA HIROMASA ,  SOMEYA IKUO ,  YOSHIMURA KOSUKE

IPC: H04H1/00 ,  H04H20/89 ,  H04H40/36 ,  H04N7/015 ,  H04N11/04 ,  H04H5/00

Abstract: PURPOSE:To perform the switching and D/A conversion of a voice output at the D/A converter IC itself by providing a circuit for performing the switching of the voice output. CONSTITUTION: -SIGMA conversion parts 5 are provided on the rear stages of digital filters DF 2 of respective channels, waveform shaping buffers 6 are provided on the front stages of low-pass filters 4, further, selectors 7a and 7b are provided on the front staves of waveform shaping buffers 6 for 3ch and 4ch, and a D/A converter IC 8 is composed of the digital filters 2, -SIGMA conversion parts 5, waveform shaping buffers 6 and selectors 7a and 7b. In this case, the combination of selections at the selectors 7a and 7b constituting the switching circuit is (7a, 7b)=(D2, D2) in the case of MUSE3-2, and it is (7a, 7b)=(D1, D1) in the case of stereo and BS modes. Thus, it can be made the same as an output system provided by performing D/A conversion to the five channels of serial data after the selections.

公开(公告)号：JPH0730779A

公开(公告)日：1995-01-31

申请号：JP19384093

申请日：1993-07-12

Applicant: SONY CORP

Inventor： SOMEYA IKUO ,  SHIMIZU AKIRA

IPC: H04N5/18

Abstract: PURPOSE:To clamp a signal, to which synchronizing information is added, at a prescribed level. CONSTITUTION:This device is provided with a rough clamp mode for supplying a first control signal from a first comparator 11 through a switch S1 to a gain control amplifier 10 to control the gain of an inputted signal and a synchronous clamp mode for supplying a second control signal to the amplifier 10 through a second comparator 12 activated by the synchronizing information. When a PLL circuit is locked to the input signal, switches S1 and S2 are switched and especially when the switch S2 is switched from the rough clamp mode to the synchronous clamp mode, however, the level of the control signal to be supplied to the gain control amplifier 10 is controlled not to be considerably fluctuated. Since the clamp operation is smoothly performed as a result, the distortion of the video signal can be reduced.

公开(公告)号：JPH06334969A

公开(公告)日：1994-12-02

申请号：JP12168693

申请日：1993-05-24

Applicant: SONY CORP

Inventor： SOMEYA IKUO ,  KOMODA MASAHIRO

IPC: H04N7/015 ,  H04N7/00 ,  H04N11/00 ,  H04N11/24

Abstract: PURPOSE:To make blur in a moving picture inconspicuous by extending the spatial frequency band of an interpolating filter in a low part of temporal frequency. CONSTITUTION:A signal from an inter-frame interpolating block 4 is supplied to a multiplier 10 through a rate conversion block 7, a low pass filter 8 and the 1st inter-field interpolating block 9. A signal from an intra-field interpolating block 5 is supplied to an adder 12 and a subtractor 13 and subtracted from the original signal and the subtracted signal is supplied to the adder 12 through the 2nd inter-field interpolating block 16. A signal from the adder 12 is supplied to a multiplier 18 through a rate conversion block 17. A movement detection signal MD from a moving area detecting circuit 6 and a control signal (1-MD) are respectively supplied to the multipliers 18, 10. Then output signals from the multipliers 10, 18 are supplied to an adder 11.

公开(公告)号：JPH06326974A

公开(公告)日：1994-11-25

申请号：JP13507493

申请日：1993-05-14

Applicant: SONY CORP

Inventor： SOMEYA IKUO

IPC: H04N5/93 ,  H04N7/00 ,  H04N7/015

Abstract: PURPOSE:To prevent the disturbance of dots regardless of the disorder of subsample sequence at the time of decoding a MUSE signal. CONSTITUTION:Frame memories 1 and 2 of 16Ms/s operation are cascaded, and the signal subjected to inter-frame interpolation processing of sample rate 32Ms/s is obtained by a switch 4 which controls switching between the present signal of sample rate 16Ms/s and the output signal of the frame memory 1 based on a control signal YSS. A signal for difference between two frames is obtained by the output signal of the frame memory 2 and the present signal. Further, the odd motion vector quantity is corrected by a latch circuit 3 provided between the switch 4 and the frame memory 1.

公开(公告)号：JPH05328170A

公开(公告)日：1993-12-10

申请号：JP15576692

申请日：1992-05-22

Applicant: SONY CORP

Inventor： SOMEYA IKUO

IPC: H04N5/14 ,  H04N7/00 ,  H04N7/015

Abstract: PURPOSE:To realize the video processor capable of preventing ringing due to impulse response and also eliminating reflected distortion. CONSTITUTION:This processor is provided with filters 2, 3 with a different characteristic used to eliminate a reflected signal included in an input video signal, filters 5, 6 detecting an amplitude of an original signal being a source of the reflected signal and a comparator 7 used to select any of the cut-off frequencies of the reflected noise elimination filters 2, 3 based on the amplitude detected by the filter 6. Thus, the generation of ringing is prevented and the frequency characteristic is improved.

公开(公告)号：JPH059989B2

公开(公告)日：1993-02-08

申请号：JP8282682

申请日：1982-05-17

Applicant: SONY CORP

Inventor： SOMEYA IKUO ,  SUEMATSU MASAYUKI ,  MATSUNAGA OSAMU

IPC: H04N5/00 ,  H04N5/44 ,  H04Q9/14

公开(公告)号：JPH0461586A

公开(公告)日：1992-02-27

申请号：JP17170490

申请日：1990-06-29

Applicant: SONY CORP

Inventor： SOMEYA IKUO

IPC: H04N7/015 ,  H04N5/16 ,  H04N5/18 ,  H04N7/00 ,  H04N7/20

Abstract: PURPOSE:To surely eliminate a dispersal signal by applying a cancel signal from a cancel signal generating circuit to a synthesis circuit so as to cancel the dispersal signal. CONSTITUTION:A digital MUSE signal in which a superimposed dispersal signal from an A/D converter 12 remains is fed to positive and negative hold circuits 19, 20 through averaging circuits 17, 18 as noise elimination circuits respectively in a residual dispersal quantity detection circuit 16. An output from a D/A converter 23 and an inverting output resulting from inverting the phase of the above output by an inverting amplifier 26 are selected for each frame by a frame pulse FP from an input terminal 25a by a changeover switch 25 and fed to an integration circuit 27, in which the selected signal is integrated and a resulting cancel signal is fed to a synthesis circuit 3.

公开(公告)号：JPH03247192A

公开(公告)日：1991-11-05

申请号：JP4519490

申请日：1990-02-26

Applicant: SONY CORP

Inventor： SOMEYA IKUO

IPC: H04N19/50 ,  H04N7/015 ,  H04N11/04 ,  H04N19/423 ,  H04N19/44 ,  H04N19/51 ,  H04N19/59 ,  H04N19/80 ,  H04N19/85

Abstract: PURPOSE:To reduce fog in a reproduced picture by providing a 3rd reproduction means applying only an inter-field interpolation to an input signal and selecting the reproduced signal from the 3rd reproduction means when a frequency of the movement of a picture element being an object of reproduction in timewise direction is nearly intermediate. CONSTITUTION:An output signal of an input block 43 in an added block 47 is fed to an inter-field interpolation block 55. The interpolation block 55 adds input signals in terms of fields and the added signal is interpolated by a filter. Thus, an intermediate picture signal whose horizontal frequency is 32MHz is reproduced. The intermediate picture signal is fed to one input port of a multiplier 56 and the output signal of the multiplier 56 is fed to other input port of an adder 54. When the processing for the intermediate picture signal of the inter-field interpolation block 55 is applied, deterioration in picture quality to some degree is generated. However, so-called excellent picture quality with less fog is obtained entirely.