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公开(公告)号：DE69123648T2
公开(公告)日：1997-04-30
申请号：DE69123648
申请日：1991-07-08
Applicant: SONY CORP
Inventor： SOMEYA IKUO , KOMODA MASAHIRO
IPC: H04N5/14 , H03H15/00 , H03H17/00 , H03H17/06 , H03H21/00 , H04B3/06 , H04L25/03 , H04N5/21 , H04N7/015 , H04N9/64 , H04N11/04
Abstract: A waveform equalizing filter unit of a simplified circuit configuration for use in a MUSE decoder or the like. The filter unit comprises a waveform equalizing filter with a plurality of taps each having a unitary delay element and a coefficient multiplier; a clock switching circuit for selecting one of clock signals of at least two different frequencies inputted thereto, and outputting the selected clock signal to the unitary delay elements of the waveform equalizing filter; and a control means for selectively switching the tap coefficients of the coefiicient multpliers in the waveform equalizing filter in accordance with the operation of switching the clock signals by the clock switching circuit. A signal timing adjuster is further included in a stage anterior to the waveform equalizing filter so as to adjust the timing to switch the input signal in synchronism with the clock switching operation. In such constitution, optimal signal waveform equalization conforming to each distortion characteristic can be achieved in a simplified circuit configuration by selectively switching both sampling rates and tap coefficients of a single waveform equalizing filter in accordance with the distortion characteristic.
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公开(公告)号：DE69123648D1
公开(公告)日：1997-01-30
申请号：DE69123648
申请日：1991-07-08
Applicant: SONY CORP
Inventor： SOMEYA IKUO , KOMODA MASAHIRO
IPC: H04N5/14 , H03H15/00 , H03H17/00 , H03H17/06 , H03H21/00 , H04B3/06 , H04L25/03 , H04N5/21 , H04N7/015 , H04N9/64 , H04N11/04
Abstract: A waveform equalizing filter unit of a simplified circuit configuration for use in a MUSE decoder or the like. The filter unit comprises a waveform equalizing filter with a plurality of taps each having a unitary delay element and a coefficient multiplier; a clock switching circuit for selecting one of clock signals of at least two different frequencies inputted thereto, and outputting the selected clock signal to the unitary delay elements of the waveform equalizing filter; and a control means for selectively switching the tap coefficients of the coefiicient multpliers in the waveform equalizing filter in accordance with the operation of switching the clock signals by the clock switching circuit. A signal timing adjuster is further included in a stage anterior to the waveform equalizing filter so as to adjust the timing to switch the input signal in synchronism with the clock switching operation. In such constitution, optimal signal waveform equalization conforming to each distortion characteristic can be achieved in a simplified circuit configuration by selectively switching both sampling rates and tap coefficients of a single waveform equalizing filter in accordance with the distortion characteristic.
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公开(公告)号：JP2006304352A
公开(公告)日：2006-11-02
申请号：JP2006169378
申请日：2006-06-19
Inventor： SOMEYA IKUO , KOMODA MASAHIRO , TAKECHI AYA
Abstract: PROBLEM TO BE SOLVED: To provide an image processor capable of improving picture quality improving an effect by widening the frequency range of enhancement processing, and also performing two-dimensional enhancement processing for an image signal by simple circuit constitution. SOLUTION: A vertical low-pass filter (160) and a vertical high-pass filter (100), and horizontal high-pass filters (110) and (170) and a horizontal low-pass filter (120) are provided as enhancers, and high-frequency components and low-frequency components are extracted vertically and horizontally. The cutoff frequency of the first horizontal filter (110) is set to ≤1/8 time as high as a sampling frequency and a roll-off rate is set to about 1.0. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提供一种能够通过加宽增强处理的频率范围来提高图像质量来提高效果的图像处理器，并且还通过简单的电路结构对图像信号进行二维增强处理。 解决方案：提供垂直低通滤波器（160）和垂直高通滤波器（100）以及水平高通滤波器（110）和（170）以及水平低通滤波器（120） 作为增强器，并且垂直和水平地提取高频分量和低频分量。 第一水平滤波器（110）的截止频率被设定为采样频率的≤1/ 8倍，并且滚降速率被设定为约1.0。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2003348580A
公开(公告)日：2003-12-05
申请号：JP2002152930
申请日：2002-05-27
Inventor： SOMEYA IKUO , KOMODA MASAHIRO , TAKECHI AYA
IPC: H04N19/126 , H04N7/01 , H04N7/24 , H04N19/00 , H04N19/134 , H04N19/136 , H04N19/137 , H04N19/174 , H04N19/186 , H04N19/196 , H04N19/50 , H04N19/85 , H04N19/90 , H04N19/98
Abstract: PROBLEM TO BE SOLVED: To suppress deterioration in image quality by adaptively performing compressive coding with a local quality in an image signal. SOLUTION: A block processing part 21 blocks the image signal DVi such that each of divided parts obtained by dividing one line into a plurality of parts becomes one block and generates a block discrimination signal BL that can partition each block. A maximum value information determining part 22 extracts an initial value P being a signal of a first pixel for each block on the basis of the image signal DVi and the discrimination signal BL and also determines maximum value information Q showing in which range the maximum value of an absolute value of a signal level difference between pixels is located. An encoding processing part 25 applies nonlinear quantization processing to a level difference signal ED between the pixels with independent nonlinear characteristic for each block to generate a compressed image signal DWi. In this case, the nonlinear characteristic is determined on the basis of coded bit length information R and the maximum value information Q inputted by a user's operation. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：通过在图像信号中以局部质量自适应地执行压缩编码来抑制图像质量的劣化。 解决方案：块处理部分21阻止图像信号DVi，使得通过将一行划分成多个部分而获得的每个分割部分变成一个块，并且生成可以对每个块进行分区的块识别信号BL。 最大值信息确定部分22基于图像信号DVi和鉴别信号BL提取作为每个块的第一像素的信号的初始值P，并且还确定最大值信息Q，其显示哪个范围的最大值 位于像素之间的信号电平差的绝对值。 编码处理部分25对每个块的独立非线性特征的像素之间的电平差信号ED应用非线性量化处理，以产生压缩图像信号DWi。 在这种情况下，基于编码位长度信息R和由用户的操作输入的最大值信息Q来确定非线性特性。 版权所有（C）2004，JPO
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公开(公告)号：JP2003046961A
公开(公告)日：2003-02-14
申请号：JP2001232661
申请日：2001-07-31
Inventor： SOMEYA IKUO , KOMODA MASAHIRO
Abstract: PROBLEM TO BE SOLVED: To realize picture display by making the deterioration of picture quality inconspicuous without increasing the scale of a horizontal deflecting circuit even at the time of using a picture signal of a format whose horizontal synchronizing frequency is different.
SOLUTION: The synchronizing signal of a picture signal Dga is detected by a synchronization detecting part 21, and the signal format of the picture signal Dga is judged by a control unit 30 based on the detected synchronizing signal. When it is judged that the judged signal format is a progressive scanning system, and the horizontal synchronizing frequency is higher than a horizontally deflectable frequency, the vertical synchronizing frequency of the picture signal Dga is changed by a signal converting part 22, and the picture signal Dga is converted into a picture signal Dgb whose horizontal synchronizing frequency is the horizontally deflectable frequency as an interlace scanning system signal, and picture display is executed by using the picture signal Dgb.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：即使在使用水平同步频率不同的格式的图像信号的时候，也不会增加水平偏转电路的尺度，使图像质量的劣化不显眼，实现图像显示。 解决方案：图像信号Dga的同步信号由同步检测部分21检测，并且图像信号Dga的信号格式由控制单元30基于检测到的同步信号来判断。 当判断出判断信号格式是逐行扫描系统，并且水平同步频率高于水平偏转频率时，图像信号Dga的垂直同步频率由信号转换部分22改变，并且图像信号 Dga被转换为水平同步频率是水平偏转频率的图像信号Dgb作为隔行扫描系统信号，并且通过使用图像信号Dgb执行图像显示。
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Patent Agency Ranking
公开(公告)号：JPH06334969A
公开(公告)日：1994-12-02
申请号：JP12168693
申请日：1993-05-24
Applicant: SONY CORP
Inventor： SOMEYA IKUO , KOMODA MASAHIRO
Abstract: PURPOSE:To make blur in a moving picture inconspicuous by extending the spatial frequency band of an interpolating filter in a low part of temporal frequency. CONSTITUTION:A signal from an inter-frame interpolating block 4 is supplied to a multiplier 10 through a rate conversion block 7, a low pass filter 8 and the 1st inter-field interpolating block 9. A signal from an intra-field interpolating block 5 is supplied to an adder 12 and a subtractor 13 and subtracted from the original signal and the subtracted signal is supplied to the adder 12 through the 2nd inter-field interpolating block 16. A signal from the adder 12 is supplied to a multiplier 18 through a rate conversion block 17. A movement detection signal MD from a moving area detecting circuit 6 and a control signal (1-MD) are respectively supplied to the multipliers 18, 10. Then output signals from the multipliers 10, 18 are supplied to an adder 11.
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公开(公告)号：JP2005086388A
公开(公告)日：2005-03-31
申请号：JP2003314950
申请日：2003-09-08
Inventor： SOMEYA IKUO , KOMODA MASAHIRO
IPC: H04N5/21
Abstract: PROBLEM TO BE SOLVED: To obtain a high quality of pictures nearly equivalent to those processed on the 10-bit base whereas they are basically processed on the 8-bit base. SOLUTION: A bit extender 35 receives input picture signals of 8 bits. An LPF 51 extracts low frequency components of the inputted picture signals and supplies them to a subtractor 52 and an adder 53. The subtractor 52 subtracts the picture signals of only the low frequency components outputted from the LPF 51 from the picture signals containing all the frequency components, and as the result, outputs the picture signals of only high frequency components from the subtractor 52, thus supplying the picture signals of high frequency components from the subtractor 52 to the adder 53 via a rounding unit 54. The adder 53 adds the supplied picture signals of the low frequency components and those of high frequency components to generate picture signals of all frequency components, and supplies them to a limiter 55. The limiter 55 checks and processes to limit the range of the supplied picture signals within which the picture signals can be handled at following stages. This is applicable to television receivers. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：为了获得几乎等同于10位基础处理的图像的高质量，而它们基本上在8位基础上被处理。 解决方案：位扩展器35接收8位的输入图像信号。 LPF51提取输入图像信号的低频分量，并将它们提供给减法器52和加法器53.减法器52从包含所有频率的图像信号中减去仅从LPF51输出的低频分量的图像信号 并且结果，从减法器52输出仅高频分量的图像信号，从而经由舍入单元54将来自减法器52的高频分量的图像信号提供给加法器53.加法器53将所提供的 低频分量的图像信号和高频分量的图像信号，以产生所有频率分量的图像信号，并将它们提供给限幅器55.限幅器55检查并处理所提供的图像信号的范围，其中图像信号 可以在以下阶段处理。 这适用于电视接收机。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2001346168A
公开(公告)日：2001-12-14
申请号：JP2000164028
申请日：2000-06-01
Applicant: SONY CORP
Inventor： SOMEYA IKUO , KOMODA MASAHIRO
IPC: H04N7/01
Abstract: PROBLEM TO BE SOLVED: To provide an image signal conversion method by which occurrence of a difference from line numbers between fields of a converted HD signal can be suppressed. SOLUTION: Whether or not an SD signal received by the image conversion system of this invention is a standard signal in compliance with the NTSC standards is discriminated on the basis of a discrimination signal received from a three-dimensional YC separation device in a step S1. In the case that the received SD signal is discriminated to be the standard signal, a standard system is decided for the synchronization system in a step S2. On the contrary, in the case that the received SD signal is discriminated to be no standard signal in the step S1, a non-standard system is decided for the synchronization system in a step S3.
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公开(公告)号：JPH10248039A
公开(公告)日：1998-09-14
申请号：JP6546597
申请日：1997-03-03
Applicant: SONY CORP
Inventor： SOMEYA IKUO , KOMODA MASAHIRO , UTSUNOMIYA HIROSHI
Abstract: PROBLEM TO BE SOLVED: To attain the reduction of memory capacity by extending a motion detecting signal, which is provided based on difference between two frames, in the direction of time base through a recursive filter provided with a field delay circuit when decoding a MUSI signal compressed by a MUSE system. SOLUTION: A still picture/moving image decode part 30 inputs a MUSE signal S21 inputted through a non-linear de-emphasis circuit and an inverse transmission gamma circuit respectively to a moving image interpolation circuit part 51, still picture interpolation circuit part 52 and motion detection part 30A. The motion detection part 30A successively inputs the input signal to field memories 31-34 and respectively delays them just for one field, and a differential circuit 61 calculates the difference between the MUSE signal delayed just for two frames and the current inputted MUSE signal S21 and provides the motion detection signal between two frames. Then, a bit conversion circuit 63 of recursive filter 30B extends this motion detection signal in the direction of time base through bit conversion.
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公开(公告)号：JPH07123371A
公开(公告)日：1995-05-12
申请号：JP28575393
申请日：1993-10-21
Applicant: SONY CORP
Inventor： KOMODA MASAHIRO , SOMEYA IKUO
Abstract: PURPOSE:To inexpensively realize the improvement of the picture quality in a motion area in a device where a television signal is transmitted by performing a sub-sampling for the signal and a decoding processing is performed by dividing areas into still areas and the motion areas at the time of a decoding. CONSTITUTION:The information on the still area of an image is reproduced from the information on plural fields by using field memories F10 to F40 in a still area processing part 10. In a motion area processing part 200, an intra-field interpolation is performed for the current signal and the signal delayed from field memories F10 and F20, an inter-field interpolation is performed by using the signals for which these intra-field interpolations are performed and the information on the motion area of the image is reproduced. At the prestage of the still picture processing part 10, a delay circuit 8 corresponding to the processing delay time alpha in the motion area processing part 200 for the still picture processing part 10 is provided. The signal where the input signal is delayed by (one field-alpha) is supplied from the field memories F10 and F20 to the motion area processing part 200. The output of the still area processing part 10 and the output of the motion area processing part 200 are synthesized according to the motion detection amount from a motion area detection means 3.
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