公开(公告)号：WO1992011597A1

公开(公告)日：1992-07-09

申请号：PCT/US1991009460

申请日：1991-12-16

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  CALDARALE, Charles, Raymond ,  DUDDA, Klaus, Gustav +di ,  HANCOCK, Peter, John

IPC: G06F12/10

CPC classification number: G06F17/30949 ,  G06F12/1018 ,  Y10S707/99931

Abstract: A method of resolving conflicts when the index values of different binary bit designators are found to be equal is provided which is implementable in a virtual memory to real memory address translation scheme and alternately in a data base environment. Binary bit designators are used, each of which consists of a first compare segment, a second index segment and a third offset segment. When two indexes are found to be identical, similar groups of bits in the first segment are considered as subsidiary indexes and are utilized in sequence until all of the bits of said first segments have been used. Each time an index operation occurs a new table entry in a new table is identified, until a group of bits from the first segments of the different binary bit designators are found to be unequal. When this occurs, comparisons of the final table entries in the final table are undertaken to determine if each stored value in each final table entry is equal to the value represented by the associated first segment.

公开(公告)号：WO1992002093A1

公开(公告)日：1992-02-06

申请号：PCT/US1991005343

申请日：1991-07-25

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  KINGSTON, Samuel, Charles ,  BARHAM, Steven, Todd ,  SIMONSEN, Harold, Lynn

IPC: H04L27/14

CPC classification number: H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057

Abstract: A present invention novel frequency-phase discriminator has input channels for real and imaginary data which are coupled to two programmable despreaders. The first despreader has its real and imaginary outputs coupled to individual programmable data rate filters which have their individual outputs coupled to a quadrant detector that generates a phase angle direction signal and sign magnitude. The second despread has its real and imaginary outputs connected through individual programmable inverters to data rate filters which have their individual outputs coupled to a quadrant selector that selects error signal data rate information from one of four quadrant axes signals. A command generator is programmably coupled to the output of the quadrant detector and to the input of the quadrant selector and provides a selection signal to the quadrant selector which produces a frequency error signal output employed in a frequency lock loop or in a phase lock loop.

公开(公告)号：WO1991006065A2

公开(公告)日：1991-05-02

申请号：PCT/US1990005676

申请日：1990-10-04

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  KLEIN, Robert ,  D'AOUST, Robert ,  GROSSE, Debora, Y. ,  REASONER, George, E., Jr. ,  WILLIAMS, David, C. ,  ROPPO, Antonette, M. ,  BRENNAN, Audrey, A. ,  JENNINGS, Kevin

IPC: G06F15/70

CPC classification number: G06T1/20 ,  G06T3/403

Abstract: An image data processor system includes a plurality of subprocessors arranged in a pipeline for carrying out functions of pixel normalization, background suppression, spot and void removal, image scaling, and size detection. Processed image data contain useful image formation data and background feature a background suppression scheme used to convert each pixel value to preselected values in a smaller range in order to facilitate data processing such as compression and scaling. The initially presented image data in the form of an array of multi-bit pixels having plural scale values are filtered. The scale value pixels are converted to an array of binary pixels in which each pixel is associated with either background or image formation data. Patterns of pixels are used to transform a center pixel in a manner to remove isolated spots or voids from the image. Processed imaged pixel data are analyzed to indicate the size of the document being scanned. Processed image pixel data permit a scaling processor to change the size of the image for further processing.

Abstract translation: 图像数据处理器系统包括布置在流水线中的多个子处理器，用于执行像素归一化，背景抑制，斑点和空白去除，图像缩放和尺寸检测的功能。 处理的图像数据包含有用的图像形成数据和背景特征背景抑制方案，用于将每个像素值转换为较小范围内的预选值，以便于诸如压缩和缩放之类的数据处理。 以具有多个比例值的多比特像素阵列的形式的初始呈现的图像数据被过滤。 缩放值像素被转换成二进制像素的阵列，其中每个像素与背景或图像形成数据相关联。 使用像素的图案来以中心像素的形式来去除孤立的斑点或空隙。 分析处理的成像像素数据以指示被扫描的文档的大小。 处理的图像像素数据允许缩放处理器改变图像的尺寸以进行进一步处理。

公开(公告)号：WO1991006064A1

公开(公告)日：1991-05-02

申请号：PCT/US1990005678

申请日：1990-10-04

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  D'AOUST, Robert ,  CORDING, Robert, B. ,  GROSSE, Debora, Y. ,  JENNINGS, Kevin ,  KREBS, Stephen, R. ,  REASONER, George, E., Jr. ,  SMITH, Gerald, R. ,  WILLIAMS, David, C. ,  CAPO, Joseph, M. ,  KLEIN, Robert ,  NIGAM, Ravi, K.

IPC: G06F15/66

CPC classification number: G06T1/20

Abstract: A pipelined image processor generates an image of the information contained on first and second portions of a document includes a first pipe for processing information contained on the first portion of the document, and second pipe for processing information contained on the second portion of the document. The pipes receive the output from two camera assemblies which are used for generating an electrical signal in response to information contained on the document. An image digitizer generates digitized information from the electrical signals both pipes also include a resequencer for generating resequenced information from the digitized information, as well as an image processor for generating processed information from the resequenced information. The first and second pipes include a transposer/compressor assembly for generating transposed and compressed information from the processed information, and a compressed data buffer for storing the transposed and compressed information. During periods of inter-document time gaps, the diagnostic testing pattern is communicated to the resequencer, image processor, and transposer/compressor assemblies in the pipelined image processor. Each of these assemblies responds to the diagnostic testing pattern and the results are sent to a diagnostic transport interface which then determines faults associated therewith.

Abstract translation: 流水线图像处理器生成包含在文档的第一和第二部分上的信息的图像包括用于处理包含在文档的第一部分上的信息的第一管道和用于处理包含在文档的第二部分上的信息的第二管道。 管道接收来自两个相机组件的输出，其用于响应于文档中包含的信息而产生电信号。 图像数字转换器从电信号产生数字化信息，两个管道还包括用于从数字化信息产生再分配信息的再同步器，以及用于从重排序信息产生经处理信息的图像处理器。 第一和第二管道包括用于从经处理的信息产生转置和压缩信息的转移器/压缩机组件，以及用于存储转置和压缩信息的压缩数据缓冲器。 在文档间时间间隔期间，将诊断测试模式传送给流水线图像处理器中的重新排序器，图像处理器和转换器/压缩器组件。 这些组件中的每一个响应于诊断测试模式，并将结果发送到诊断传输接口，然后诊断传输接口确定与之相关联的故障。

公开(公告)号：WO1991006052A2

公开(公告)日：1991-05-02

申请号：PCT/US1990005671

申请日：1990-10-04

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  BENKARSKI, Michael, T. ,  BOONE, Donald, A. ,  ROGAN, James, D. ,  KERN, Norman, P. ,  GEORGE, Kevin, A. ,  CAPO, Joseph, M. ,  WIKEN, Morten ,  GREEN, Howard, H. ,  PALGUT, Karen, M. ,  FORBES, Brian, K. ,  HEMMANN, John, G. ,  RAO, Venkat, V.

IPC: G06F09/44

CPC classification number: G06Q40/02 ,  G06F17/30017

Abstract: An image-based document processing system comprised of a plurality of hardware components (Fig. 1) arranged as a platform for processing documents using document images. The system employs layered software architecture (Figs. 8-10) comprised of application programs, system services and a plurality of native operating systems provided for particular ones of the hardware components. The system services are callable by the application programs to provide an interface between the application programs and the native operating systems during operation of the system. A host computer (Fig. 1, 34) provides for operation of the system such that a document processor (Fig. 1, 3) captures images of documents while the documents are sorted into pockets (32a). The captured images are applied via a high throughout optical network (41) for storage on a storage and retrieval unit (42). Image workstations (50) retrieve the stored for viewing and entering of data from the document images, following which, the documents are taken to a power encoder (60) which encodes data on the documents based on the viewed document images.

Abstract translation: 一种基于图像的文档处理系统，其包括多个硬件组件（图1），其被布置为用于使用文档图像处理文档的平台。 该系统采用由应用程序，系统服务和为特定硬件组件提供的多个本地操作系统组成的分层软件体系结构（图8-10）。 系统服务可由应用程序调用，以便在系统操作期间在应用程序和本地操作系统之间提供接口。 主计算机（图1，34）提供系统的操作，使得文档处理器（图1,3）在将文档分类到口袋（32a）中时捕获文档的图像。 捕获的图像通过高整个光网络（41）施加以存储在存储和检索单元（42）上。 图像工作站（50）从文档图像中检索存储的数据的查看和输入，随后将文档带到基于所查看的文档图像对文档上的数据进行编码的功率编码器（60）。

公开(公告)号：WO1991002412A1

公开(公告)日：1991-02-21

申请号：PCT/US1990004405

申请日：1990-08-06

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  HOFFMAN, Philip, Matthew

IPC: H03M07/46

CPC classification number: G06T9/005 ,  H03M7/3088 ,  H03M7/46

Abstract: A data compression/decompression system employs two stages of data compression. Information and/or character data is first formatted into M-bit width digital data characters for input to the first stage of the data compression system which comprises an expanding run length encoder (63) having N-bit width output character where N>M and the number of M-bit width characters is greater than the number of N-bit width characters. The output of the expanding run length encoder (63) is applied directly to a compatible adaptive string matching second stage data compression encoder (65) of the type which is not degraded or affected by the input. When the input data stream to the two stage system is not of a known format or provided with leader or header bit character width information, a bit analyzer (54) and a chopper (59, 61) are provided in the data stream to prepare the data stream in a bit character width format which matches the input of the expanding run length encoder (63).

公开(公告)号：WO1990010343A1

公开(公告)日：1990-09-07

申请号：PCT/US1990000755

申请日：1990-02-09

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  PROTOPAPAS, Dimitrios

IPC: H04J03/16

CPC classification number: H04J3/1629

Abstract: A frame building procedure for use in time division multiplexer systems for building a frame with N slots numbered #1, #2, #3,..., #N in increasing time order. A slot assignment sequence is generated in successive iterations I by initially assigning slot #1 as the first assignment in the sequence (50). N/2x is added to the slot number of all previously assigned slots during each iteration (54). Additionally, during each iteration, I is incremented by unity (59). The iterations are performed until all N slots are assigned when N/2x = 1 (58).

公开(公告)号：WO1990003045A1

公开(公告)日：1990-03-22

申请号：PCT/US1989004003

申请日：1989-09-15

Applicant: UNISYS CORPORATION ,  PACIFIC TREATMENT CORPORATION

Inventor： UNISYS CORPORATION ,  PACIFIC TREATMENT CORPORATION ,  CURTIS, Robert, David ,  HORNER, James, William ,  NORELL, Ronald, Allen ,  ZABLOTNY, Gordon, Olivier

IPC: H01L21/48

CPC classification number: H01L21/4807 ,  H05K1/0306 ,  H05K3/0017

Abstract: A method of forming holes in the unfired ceramic layers of integrated circuit packages. Via holes (12 of Fig. 1) in a thin planar layer of unfired ceramic (10' of Fig. 1), which consists essentially of a mixture of an inorganic nonmetallic powder having a high melting temperature and a binder having a lower vaporizing temperature, are formed by the steps of: direting a laser beam (22a of Fig. 2), in a sequence, at certain locations on the layers (30a of Fig. 2) where the via holes are to be formed; controlling the power density in the directed laser beam to a low level at which the binder vaporizes at each of the locations while the power stays unsintered and unmelted (as per Fig. 3); and removing (by means of 25 and 26 of Fig. 2) from the directed laser beam during the above steps, both the vaporized binder and the unbound powder which remains where the binder vaporizes. Preferably, the vaporizing temperature of the binder and the melting temperature of the powder are selected such that they differ by at least 200 DEG C; the power density of the laser is controlled to be between 5kW/cm and 75kW/cm ; and the removing step is performed by impinging a gas jet at each location where the laser beam is directed and simultaneously vacuuming the location.

Abstract translation: 一种在集成电路封装的未焙烧陶瓷层中形成孔的方法。 通孔（图1中的12）位于未焙烧陶瓷（图1的10'）的薄平坦层中，其基本上由具有较高熔融温度的无机非金属粉末和具有较低蒸发温度 通过以下步骤形成：在要形成通孔的层（图2的30a）上的某些位置处，依次导向激光束（图2的22a）; 将定向激光束中的功率密度控制在低水平，在此处，当粘合剂在每个位置蒸发时，功率保持未烧结和未熔化（如图3所示）; 并且在上述步骤中，通过定向激光束去除（借助于图2的25和26），蒸发的粘合剂和残留在粘合剂蒸发的未结合的粉末。 优选地，选择粘合剂的蒸发温度和粉末的熔融温度使其相差至少200℃; 激光器的功率密度控制在5kW / cm 2和75kW / cm 2之间; 并且通过在激光束被引导的每个位置处冲击气体射流并且同时抽吸该位置来执行去除步骤。

公开(公告)号：WO1990001235A1

公开(公告)日：1990-02-08

申请号：PCT/US1989003143

申请日：1989-07-21

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  KEATE, Christopher, Raymond ,  THORNOCK, Jeffrey, Mac

IPC: H04L27/22

CPC classification number: H04L27/2273

Abstract: A phase detector for a multi-channel PSK receiver is provided with a plurality of phase channels (X, Y). Each of the phase channels has its own comparator (56, 57) coupled to an electronic switch (58, 63) for producing signals which are the products of the analog data inputs on the phase channels. The outputs from the electronic switches (58, 63) are connected to positive (61) and negative (60) summing circuits and the output of the positive and negative summing circuits are connected to the positive (72) and negative (71) inputs of a differential amplifier (68) which produce a sum of the difference of the absolute value of the analog data inputs which is employed as an error voltage signal to control the frequency of a voltage controlled oscillator (not shown) in a multi-channel PSK receiver. By eliminating convention analog multipliers in the phase detector, the phase detector is capable of generating error voltage signals from analog data input signals having data rates as high as 5 gigabytes per second.

公开(公告)号：WO1990000783A1

公开(公告)日：1990-01-25

申请号：PCT/US1989003049

申请日：1989-07-12

Applicant: UNISYS CORPORATION ,  KERYHUEL, Alain

Inventor： UNISYS CORPORATION

IPC: G07F07/10

CPC classification number: G07F7/1008 ,  G06K7/0021 ,  G06K7/0086 ,  G06K19/07 ,  G06K19/077 ,  G06K19/07703 ,  G06Q20/346

Abstract: A system provides a card (24) whereon a keyboard (72) is provided. The card (24) has contacts (80) on the rear thereof. The card (24) is brought into electrical contact with apparatus requiring use of a keyboard (72). Three embodiments are given, firstly, an automatic teller unit (10), secondly, a transfer terminal (188) for transferring funds between cards, and thirdly, a telephone (256). Each card (24) is provided with a money memory wherefrom numbers can be subtracted in payment or whereto numbers may be added to effect payment to the card (24). Each card is capable of a validation process whereby numbers entered on the card keyboard (72) are compared with a secret number stored in an inaccessible read-only memory (78) and the results of comparison between the keyboard (72) entered sequence and the stored number provided to the outside apparatus. The card (24) is provided with a delay between successive instances of attempts to enter the personal identification number thereby to slow down the process of trial and error of discovery of a personal identification number.