公开(公告)号：WO1998011485A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016141

申请日：1997-09-10

Applicant: UNISYS CORPORATION ,  NICHOLAS, Ronald, M.

Inventor： UNISYS CORPORATION

IPC: G06F09/44

CPC classification number: G06F8/78 ,  Y10S707/99934 ,  Y10S707/99942

Abstract: Apparatus and methods for revising a field in computer program code. One method (1) includes analyzing program code lines (2) for the presence of the field (3) and, if present, selectively revising (6) the field from the first value range to a second value range. The field has a storage attribute of n bits, where n is at least eight bits; with the first value range being inclusively between zero and 99, and the second value range being inclusively between zero and 2?n?-1. The method can further include inserting an extended field (22) representative of a base value into the program code, with the field being encoded as an offset value relative to the extended field. The method also can include creating a program code executable on a computer from the revised computer program code. The present invention also provides a system (110) for revising a computer program file (111) having multiple host language statements (112), including an analyzer (114), for identifying a preselected data type the host language statements, and a translator (115) for selectively modifying the preselected data type from the first attribute value range to a second attribute value range. The translator, alone or in combination with the analyzer, can be a code interpreter, a debugger, a code emulator, or a compiler.

Abstract translation: 用于修改计算机程序代码中的字段的装置和方法。 一种方法（1）包括分析用于场（3）的存在的程序代码行（2），并且如果存在，则将该字段从第一值范围选择性地修改（6）到第二值范围。 该字段具有n位的存储属性，其中n至少为8位; 其中第一值范围包括在零和99之间，并且第二值范围包括在零和2≤n≤-1之间。 该方法还可以包括将表示基本值的扩展字段（22）插入到程序代码中，其中该字段被编码为相对于扩展字段的偏移值。 该方法还可以包括从修改的计算机程序代码创建可在计算机上执行的程序代码。 本发明还提供了一种用于修改具有多个主机语言语句（112）的计算机程序文件（111）的系统（110），包括用于识别主机语言语句的预选数据类型的分析器（114）和翻译器 115），用于从第一属性值范围选择性地修改预选数据类型到第二属性值范围。 翻译器，单独或与分析器组合可以是代码解释器，调试器，代码仿真器或编译器。

公开(公告)号：WO1997023042A1

公开(公告)日：1997-06-26

申请号：PCT/US1996019672

申请日：1996-12-13

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  ROTHENBERGER, Roland, D. ,  SULLIVAN, Greg, T. ,  TUNG, Kenny, Y.

IPC: H03K05/13

CPC classification number: G11C7/22 ,  H03K5/133 ,  H03K5/135

Abstract: A precision delay circuit in an integrated circuit chip includes a transistor switching circuit (20) in combination with a control circuit (30) and a compensation circuit (40). The transistor switching circuit (20) receives an input signal (Vi); and in response, the transistors (20a, 20b) switch on and off at an unpredictable speed to generate an output signal (20) with a delay that has a large tolerance. The control circuit (30) estimates the unpredictable speed at which the transistors switch and it generates control signals (SL, MED, FA) that identify the estimated speed. The compensation circuit receives the control signals from the control circuit; and in response, it selectively couples (via 41-46) compensation components to the transistor switching circuit such that the combination of the transistors and the selectively coupled components generates the output signal with a precise delay.

Abstract translation: 集成电路芯片中的精密延迟电路包括与控制电路（30）和补偿电路（40）组合的晶体管开关电路（20）。 晶体管开关电路（20）接收输入信号（Vi）; 并且作为响应，晶体管（20a，20b）以不可预测的速度接通和断开，以产生具有大容差的延迟的输出信号（20）。 控制电路（30）估计晶体管切换的不可预测速度，并产生识别估计速度的控制信号（SL，MED，FA）。 补偿电路从控制电路接收控制信号; 并且作为响应，它选择性地（通过41-46）补偿组件耦合到晶体管开关电路，使得晶体管和选择耦合组件的组合以精确的延迟产生输出信号。

公开(公告)号：WO1997011491A1

公开(公告)日：1997-03-27

申请号：PCT/US1996015043

申请日：1996-09-20

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  LAYTON, Wilbur, Terry ,  NORELL, Ronald, Allen ,  ROECKER, James, Andrew

IPC: H01L23/373

CPC classification number: H01L23/3733 ,  H01L23/3736 ,  H01L23/433 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat transfer module (Fig. 1) comprises: a heat generating unit (11) and a heat receiving unit (15) which are separated by a gap (space between 11 and 15); a compliant body (12), having microscopic voids therethrough, which is compressed into the gap; and a liquid metal alloy (12a and 12b in Figs. 2B and 2C) that is absorbed in the microscopic voids in the compliant body (12). Further, the heat transfer module also includes a seal ring (13) in the gap which surrounds the compliant body and which is spaced apart from the compliant body; and, the compliant body is intentionally compressed (Figs. 2B and 2C) so much that a portion of the liquid metal alloy is squeezed from the compliant body into the space between the compliant body and the seal ring. Squeezing liquid metal alloy from the compliant body lowers the thermal resistance (R>T

Abstract translation: 传热模块（图1）包括：由间隙（11和15之间的间隔）隔开的发热单元（11）和热接收单元（15）; 柔性体（12），其具有通过其的微小空隙，其被压缩到所述间隙中; 以及吸收在柔性体（12）中的微小空隙中的液态金属合金（图2B和2C中的12a和12b）。 此外，传热模块还包括在间隙中的密封环（13），该密封环围绕柔顺体并与柔顺体间隔开; 并且，柔性体被有意地压缩（图2B和2C），使得液体金属合金的一部分从柔性体被挤压到顺应性主体和密封环之间的空间中。 从柔性体中挤压液态金属合金通过增加热量传递的面积来降低发热单元（11）和热量接收单元（15）之间的热阻（R> T <表1） 通过柔性体的导热性。

公开(公告)号：WO1996036145A1

公开(公告)日：1996-11-14

申请号：PCT/US1996007741

申请日：1996-05-08

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  HARRIS, Johnny, Michael ,  GIALLORENZI, Thomas, Robert ,  MATOLAK, David, William ,  GRIFFIN, Dan, Michael

IPC: H04J11/00

CPC classification number: H04B1/62

Abstract: An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated such the output signal has a large magnitude when the input signal has a high probability of occurrence, and the output signal has a small magnitude when the input signal has a low probability of occurrence. The distorted output signal travels over a communication channel to a receiver circuit which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.

Abstract translation: 电子数据传输系统通过包括接收输入信号的发射机电路并且响应于产生失真的输出信号而具有低的峰均功率比。 产生失真的输出信号，当输入信号的发生概率很高时，输出信号的幅度大，当输入信号的发生概率低时，输出信号的幅度小。 失真的输出信号通过通信信道传播到接收机电路，接收机电路通过以与产生失真信号的增益相反的增益放大失真的输出信号来再生输入信号。

公开(公告)号：WO1996005669A1

公开(公告)日：1996-02-22

申请号：PCT/US1995010409

申请日：1995-08-15

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  GIALLORENZI, Thomas, Robert ,  RAFTER, Mark, Thomas ,  GREENWOOD, Kenneth, Clayton ,  PRESS, Harry, Baron ,  KINGSTON, Samuel, Charles

IPC: H04J13/00

CPC classification number: H04J13/00 ,  H04B1/7085 ,  H04B1/7103 ,  H04B2201/709709 ,  H04J3/0682 ,  H04J14/005

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations (TS1, TS2, TS3) and a single CDMA receiving station (RS), all of which are intercoupled to each other over one CDMA channel (FB1) and one feedback channel (FB2). On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals (21, 22, 23 of fig. 2) to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal (RCK) and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals (ER1, ER2 in 27 of fig. 2) which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization (24, 25, 26 of fig. 2) with the reference clock signal. This synchronization enables interference between the spreading codes at the receiving station to be reduced by using codes which have minimal cross-correlation when their time difference is zero; and consequently, the maximum number of stations that can simultaneously transmit is increased.

Abstract translation: 多点对点CDMA通信系统包括多个CDMA发射站（TS1，TS2，TS3）和单个CDMA接收站（RS），它们都通过一个CDMA信道（FB1）相互耦合，一个 反馈通道（FB2）。 在一个CDMA信道上，多个CDMA发送站同时向接收站发送各自的CDMA信号（图2的22,22,23）。 在接收站中，在参考时钟信号（RCK）和来自每个CDMA发射站的CDMA信号中的扩展码之间测量各自的时间差; 并且这些时间差在CDMA接收站在反馈信道上发送到每个CDMA发射站的各个误差信号（图2的27中的ER1，ER2）中指示。 每个CDMA站通过对其扩展码进行时移来响应其误差信号，使得其与参考时钟信号同步（图2的24,26,26）到达接收站。 该同步使得当它们的时间差为零时，通过使用具有最小互相关的代码来减少接收站处的扩展码之间的干扰; 因此，可以同时发送的站的最大数量增加。

公开(公告)号：WO1995018408A1

公开(公告)日：1995-07-06

申请号：PCT/US1994014929

申请日：1994-12-28

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  FLORA, Laurence, P.

IPC: G06F09/28

CPC classification number: G06F9/265 ,  G06F9/28

Abstract: High speed instruction execution apparatus is disclosed which provides multistage pipelining and branch prediction in a manner which permits speculative changes of state to be made during execution of a predicted instruction before the correctness of the prediction has been determined.

Abstract translation: 公开了一种提供多级流水线和分支预测的高速指令执行装置，其能够在确定预测的正确性之前允许在执行预测指令期间进行状态的推测性改变。

公开(公告)号：WO1994012928A1

公开(公告)日：1994-06-09

申请号：PCT/US1993011196

申请日：1993-11-20

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  FLORA, Laurence, P.

IPC: G06F07/52

CPC classification number: G06F7/5318

Abstract: A Wallace-type binary tree multiplier (Fig. 3) in which the partial products (Fig. 2) of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels (L1, L2, L3, L4, Fig. 3) comprised of full and half adders (FA, HA, Fig. 3). This reduction continues until a final set of inputs (Level L4, Fig. 3) is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder (20) and a carry lookahead adder (21) to produce the desired product (po-p15). The additions at leach level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder (20) and carry lookahead adder (21) are chosen to further enhance speed while reducing required chip area. A still further enhancement in multiplier operating speed is achieved by providing connections to adders (Fig. 3) so as to take advantage of the different times of arrival of the inputs to each level (levels L1, L2, L3, L4 in Fig. 3) along with different adder input-to-output delays.

Abstract translation: 产生被乘数和乘法器的部分乘积（图2）的Wallace型二叉树乘法器（图3），然后使用多个加法器级（L1，L2，L3，L4，图 3）由全加和半加成（FA，HA，图3）组成。 这种减少持续到产生最后一组输入（图3的等级L4），其中不超过两个输入仍然被添加到任何列中。 然后使用串行加法器（20）和进位前瞻加法器（21）来添加该最终集合以产生期望的乘积（po-p15）。 根据规定的规定执行浸出水平的添加，以提供最快的总体操作速度和最小所需的芯片面积。 此外，选择串行加法器（20）和进位先行加法器（21）的长度以进一步增强速度同时减少所需的芯片面积。 通过提供与加法器的连接（图3）来实现乘法器操作速度的进一步增强，以便利用输入到每个级别的不同时间（图3中的级别L1，L2，L3，L4） ）以及不同的加法器输入到输出延迟。

公开(公告)号：WO1994007198A1

公开(公告)日：1994-03-31

申请号：PCT/US1993008945

申请日：1993-09-21

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  HASHEMI, Seyed, Hossein ,  SEFIDVASH, Khorvash

IPC: G06F11/20

CPC classification number: G06F11/201 ,  G06F11/2015 ,  G06F11/2089 ,  G06F13/122 ,  Y02D10/14

Abstract: A mass storage/retrieval module for controlling the storage and retrieval operations of massive amounts of data in peripheral devices such as tape, disk, optical, etc. (70) provides for a buffer memory system (24c, 24d) in each of the interface control modules (8c, 8d) which permit simultaneous and concurrent writing to buffer storage (24c, 24d) and reading out of buffer storage through multiple ports (P0, P1, P2, P3) for high rates of data transfer operations. Redundancy and high reliability is provided in that each module of the system has dual busses (6a, 6b) and live replacement units such that, upon failure, an alternate unit can carry the circuitry requirements until the failing unit has been replaced.

Abstract translation: 大容量存储/检索模块，用于控制诸如磁带，磁盘，光学等的外围设备中的大量数据的存储和检索操作（70）提供了每个接口中的缓冲存储器系统（24c，24d） 控制模块（8c，8d），其允许同时并行写入缓冲存储器（24c，24d），并通过多个端口（P0，P1，P2，P3）读出缓冲存储器以实现高数据传输操作。 提供了冗余和高可靠性，因为系统的每个模块具有双总线（6a，6b）和实时更换单元，使得在故障时，备用单元可以承载电路要求，直到故障单元被更换为止。

公开(公告)号：WO1993018610A1

公开(公告)日：1993-09-16

申请号：PCT/US1993002005

申请日：1993-03-05

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  GOLDHAGEN, Bruce ,  RECANT, Michael, S. ,  HEILEMAN, David, W., Jr. ,  KRUESI, Frederick, C.

IPC: H04N01/32

CPC classification number: H04N1/32411 ,  H04M3/5307 ,  H04N1/00281 ,  H04N1/324 ,  H04N1/32566

Abstract: A voice Telephone Network Application Platform (NAP) (10) is enhanced to manage facsimile messages, as well as voice messages, by the addition of facsimile functionality (103, 104) to the platform actuatable by high-level facsimile commands (160) from applications supported on the platform. The commands include sending and receiving facsimile messages. A PC facsimile processor (FP) (104), interfacing between the platform and the telephone network (12), stores facsimile messages received from the network and facsimile messages for transmission to the network on hard disk (181). A facsimile command (160) from an application is expanded into NAP commands (162) for controlling the platform and FP commands (161) for controlling the facsimile processor so as to perform the facsimile functionality associated with the facsimile command. A recovery process utilizing a Recovery Token prevents facsimile messages from becoming lost between receipt at the FP and storage in the platform.

Abstract translation: 增强语音电话网络应用平台（NAP）（10）以通过将传真功能（103,104）添加到由高级传真命令（160）可激活的平台来管理传真消息以及语音消息 在平台上支持的应用程序。 这些命令包括发送和接收传真消息。 在平台和电话网络（12）之间接口的PC传真处理器（FP）（104）存储从网络接收的传真消息和传真消息，以传输到硬盘上的网络（181）。 来自应用的传真命令（160）被扩展为用于控制平台的NAP命令（162）和用于控制传真处理器的FP命令（161），以便执行与传真命令相关联的传真功能。 使用恢复令牌的恢复过程防止传真消息在FP的接收和平台中的存储之间丢失。

公开(公告)号：WO1993012441A1

公开(公告)日：1993-06-24

申请号：PCT/US1992010913

申请日：1992-12-16

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  RUBIN, William, W.

IPC: G01S13/95

CPC classification number: G01W1/00 ,  G01S13/951 ,  Y02A90/18

Abstract: A weather surveillance apparatus utilizes a set of beams in an elevation angular sector, one beam being offset from the other by a predetermined offset angle. Radar signal returns in each beam are processed to establish an average doppler frequency shift for the signals in the respective beams. An average of the averages and a difference of the averages are determined which are utilized to establish horizontal and vertical wind velocities. These velocities are further processed to determine whether a microburst precursor exists and the location, magnitude, time to impact, and track of any resulting windshear.