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公开(公告)号:US20200266335A1
公开(公告)日:2020-08-20
申请号:US16297704
申请日:2019-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
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公开(公告)号:US20200227625A1
公开(公告)日:2020-07-16
申请号:US16261524
申请日:2019-01-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yi-Wei Tseng , Meng-Jun Wang , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang , Yu-Ping Wang , Chien-Ting Lin , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , I-Ming Tseng
Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
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公开(公告)号:US09711368B2
公开(公告)日:2017-07-18
申请号:US13862484
申请日:2013-04-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Lung-En Kuo , Po-Wen Su , Chen-Yi Weng , Hsuan-Hsu Chen
IPC: H01L21/308 , H01L21/66 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L29/78 , H01L21/311
CPC classification number: H01L21/3086 , H01L21/31116 , H01L21/823431 , H01L21/823821 , H01L22/12 , H01L22/20 , H01L22/26 , H01L29/66795 , H01L29/785
Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.
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公开(公告)号:US09117909B2
公开(公告)日:2015-08-25
申请号:US14470957
申请日:2014-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Lung-En Kuo , Po-Wen Su , Chen-Yi Weng , Hsuan-Hsu Chen
IPC: H01L29/78 , H01L21/762 , H01L29/66 , H01L27/088 , H01L29/06
CPC classification number: H01L29/7851 , H01L21/76224 , H01L21/823431 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/7853
Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
Abstract translation: 提供一种形成翅片结构的方法。 首先,提供衬底,其中第一区域,包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后,在第一区域和第二区域中形成具有第一深度的多个第一沟槽,其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后,加深第一沟槽以形成具有第二深度的多个第二沟槽,其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。
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公开(公告)号:US20140308761A1
公开(公告)日:2014-10-16
申请号:US13862484
申请日:2013-04-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Lung-En Kuo , Po-Wen Su , Chen-Yi Weng , Hsuan-Hsu Chen
IPC: H01L21/308 , H01L21/66
CPC classification number: H01L21/3086 , H01L21/31116 , H01L21/823431 , H01L21/823821 , H01L22/12 , H01L22/20 , H01L22/26 , H01L29/66795 , H01L29/785
Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.
Abstract translation: 提供侧壁图像传送(SIT)处理。 首先,提供基板。 在衬底上形成具有图案的牺牲层。 执行第一测量步骤以测量牺牲层的图案的宽度。 材料层在牺牲层上共形地形成,其中根据第一测量步骤的结果调整材料层的厚度。 然后,各向异性地去除材料层,因此材料层成为牺牲层的侧壁上的间隔物。 最后,去除牺牲层。
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公开(公告)号:US20140306272A1
公开(公告)日:2014-10-16
申请号:US13863393
申请日:2013-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Lung-En Kuo , Po-Wen Su , Chen-Yi Weng , Hsuan-Hsu Chen
IPC: H01L21/762 , H01L29/78
CPC classification number: H01L29/7851 , H01L21/76224 , H01L21/823431 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/7853
Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
Abstract translation: 提供一种形成翅片结构的方法。 首先,提供衬底,其中第一区域,包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后,在第一区域和第二区域中形成具有第一深度的多个第一沟槽,其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后,加深第一沟槽以形成具有第二深度的多个第二沟槽,其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。
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公开(公告)号:US12290005B2
公开(公告)日:2025-04-29
申请号:US18679437
申请日:2024-05-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号:US20250107454A1
公开(公告)日:2025-03-27
申请号:US18976359
申请日:2024-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
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公开(公告)号:US12262647B2
公开(公告)日:2025-03-25
申请号:US18592553
申请日:2024-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
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公开(公告)号:US20250048936A1
公开(公告)日:2025-02-06
申请号:US18919382
申请日:2024-10-17
Applicant: United Microelectronics Corp.
Inventor: Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
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