Abstract:
PROBLEM TO BE SOLVED: To increase yield by providing a mounting method using a frame reducing the possibility of frame cracks generated when mounting a transparent substrate on a chip. SOLUTION: The active region 322 of the chip 320 has a functional region 322a. The frame 330 is formed on the mounting face of the transparent substrate 310 or the active region of the chip 320. Next, the mounting face 312 of the transparent substrate 310 is mounted on the active region 322 of the chip by the frame 330 under negative pressure. Finally, the frame 330 is solidified. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a digital cellular phone system capable of setting a group by a user, and to provide a portable telephone used by the system. SOLUTION: When registration is notified to the digital cellular phone system, it can be determined whether a member in the group is within the communication area of a base station that is the same as the user or is adjacent to the user. When the member in the group is within the communication area of the base station that is the same as the user, notification to the user is made by short message service. Additionally, when the member in the group is in the communication area of the station that is the same as the user, the user can register position information on the member and the distance between the user and the member. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a method and a device for forming a pattern type photoresist layer capable of shortening a cycle time and a re-processing time in a pattern transfer process. SOLUTION: The forming method of the pattern type photoresist layer matched with a predetermined wafer layer is provided. The photoresist layer is formed on a substrate and exposed. An overlaid offset between the exposed part of the photoresist layer and the predetermined wafer layer is measured to determine whether the exposed part of the photoresist layer matches with the predetermined wafer layer or not. A development stage is effected in the case that the exposed part of the photoresist layer matches with the predetermined wafer layer. A device is also provided for forming the pattern type photoresist layer. This device feedbacks immediately the overlaid offset utilizing the method, whereby the cycle time and the re-processing time in the pattern transfer process are shortened. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide the structure of a porous low dielectric constant material thin film and related manufacturing method for solving various problems associated with the conventional technology. SOLUTION: The method of manufacturing the porous low dielectric constant material thin film includes processes of: (a) preparing a substrate; (b) conducting a first chemical vapor deposition (CVD) process, and introducing a backbone precursor into a deposition chamber to form an interfacial dielectric layer on the substrate; (c) conducting a second CVD process, introducing a porogen precursor into the deposition chamber while at the same time introducing a backbone precursor, and combining the porogen precursor with the backbone precursor to form a backbone layer containing porogen on the interfacial dielectric layer; and (d) removing the porogen out of the backbone layer to form an ultralow dielectric constant material layer having a plurality of pores. The interfacial dielectric layer and the ultralow dielectric constant material layer constitute the porous low dielectric constant material thin film. COPYRIGHT: (C)2008,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a bevel gradient dichroic film, used in an off-axis type LCOS (liquid crystal on silicon) display device. SOLUTION: The bevel gradient dichroic film is equipped with a dichroic film having film characteristics, including gradient direction. The gradient direction depends on the incident angle of incident light so as to provide the optical characteristics that the light spots of the incident light on the dichroic film are distributed uniformly. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To enhance rubbing performance by decreasing the defects of rubbing and to prolong the lifetime of a roller and to improve the efficiency of rubbing in a rubbing process. SOLUTION: The rubbing device further has a conditioning roller, in addition to the rubbing roller, so as to promptly restore the rubbing roller in order to prolong the lifetime of the roller and to improve the efficiency of rubbing in a rubbing process. The rubbing device employs the conditioning roller in addition to the rubbing roller in such a manner, and as a result thereof, the rubbing device eventually newly includes a conditioning process for adjusting the rubbing roller in the rubbing process. The cycle time of manufacturing can be thereby shortened and productivity can be improved. COPYRIGHT: (C)2004,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a high-performance integrated circuit, particularly an integrated circuit with air gaps that fully supports metal interconnection, for the solution of problems associated with the prior art. SOLUTION: The structure of the integrated circuit comprises: a substrate 11 with an underlayer 12; the first metallic pattern 13 formed in the underlayer; the second metallic layer 17 formed above the first metallic pattern; a supporting structure with an isotropic-etched dielectric layer 14 that supports the second metallic pattern formed between the first metallic pattern and the second metallic pattern; and multiple air gaps 18a formed in a gap in the second metallic pattern that is composed of a capping layer 19. COPYRIGHT: (C)2004,JPO
Abstract:
PROBLEM TO BE SOLVED: To provide a method of manufacturing a self-alignment transistor, which can simplify the manufacturing process and reduce costs in the manufacturing process. SOLUTION: In the method of manufacturing a self-alignment bipolar transistor on a substrate 200 including an epitaxial layer 202, a first insulating layer 204 and a second insulating layer 206 are sequentially formed, and an opening is formed in the second insulating layer. On the sidewall of this opening, a conductive spacer 210 is formed, and using the second insulating layer and conductive spacer as a mask, the first insulating layer within the opening is removed. Then a conductive layer 212 as an emitter is formed within the opening, and then the second insulating layer is completely removed. This emitter is subjected to doping. Using the emitter and the conductive spacer as a mask, one portion of the first insulating layer is removed, and using the emitter and conductive spacer as a mask, the epitaxial layer is subjected to different doping to change one portion of the layer into a base contact region 218. COPYRIGHT: (C)2004,JPO
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double-damascene process which exhibits a wide process flexibility and can be easily adapted in mass-production process. SOLUTION: After an etch stop layer 54 is patterned for forming an opening 72 corresponding to a pattern in a connection which is formed on the first level of a two-level connection structure, an intermetallic dielectric layer 58 is provided on it and a photoresist mask 62 is provided on it. Openings 64 and 66 of the mask 62 correspond to the wiring pattern provided on the second level of the connection structure and a dielectric layer 58 is partially exposed from them. The dielectric layer 58 is etched and the etching is advanced in such a way that an opening 68 is produced in the exposed part of the stop layer 54 from the opening 72 of the interlayer dielectric layer 52. In other words, openings for both of the wiring on the second level and the connection on the first level are demarcated by a single etching process. Further, the opening 72 of the stop layer is tapered with its upper diameter being larger than its lower diameter. COPYRIGHT: (C)2003,JPO