Method for mounting chip on a substrate by using frame
    1.
    发明专利
    Method for mounting chip on a substrate by using frame 审中-公开
    通过使用框架在基板上安装芯片的方法

    公开(公告)号:JP2005166880A

    公开(公告)日:2005-06-23

    申请号:JP2003402641

    申请日:2003-12-02

    Abstract: PROBLEM TO BE SOLVED: To increase yield by providing a mounting method using a frame reducing the possibility of frame cracks generated when mounting a transparent substrate on a chip.
    SOLUTION: The active region 322 of the chip 320 has a functional region 322a. The frame 330 is formed on the mounting face of the transparent substrate 310 or the active region of the chip 320. Next, the mounting face 312 of the transparent substrate 310 is mounted on the active region 322 of the chip by the frame 330 under negative pressure. Finally, the frame 330 is solidified.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:通过提供使用框架的安装方法来提高产量,该框架减少了将透明基板安装在芯片上时产生的框架裂纹的可能性。 解决方案:芯片320的有源区域322具有功能区域322a。 框架330形成在透明基板310的安装面或芯片320的有源区域上。接下来,透明基板310的安装面312由框架330在负极下安装在芯片的有源区域322上 压力。 最后,框330被固化。 版权所有(C)2005,JPO&NCIPI

    Digital cellular phone system and portable telephone used therefor
    2.
    发明专利
    Digital cellular phone system and portable telephone used therefor 审中-公开
    数字蜂窝电话系统及其使用的便携式电话

    公开(公告)号:JP2005167542A

    公开(公告)日:2005-06-23

    申请号:JP2003402640

    申请日:2003-12-02

    Inventor: SEN MEICHI

    Abstract: PROBLEM TO BE SOLVED: To provide a digital cellular phone system capable of setting a group by a user, and to provide a portable telephone used by the system.
    SOLUTION: When registration is notified to the digital cellular phone system, it can be determined whether a member in the group is within the communication area of a base station that is the same as the user or is adjacent to the user. When the member in the group is within the communication area of the base station that is the same as the user, notification to the user is made by short message service. Additionally, when the member in the group is in the communication area of the station that is the same as the user, the user can register position information on the member and the distance between the user and the member.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:提供能够由用户设置组的数字蜂窝电话系统,并提供由系统使用的便携式电话。 解决方案:当向数字蜂窝电话系统通知注册时,可以确定组中的成员是否在与用户相同或与用户相邻的基站的通信区域内。 当组中的成员在与用户相同的基站的通信区域内时,通过短消息服务向用户通知。 此外,当组中的成员在与用户相同的站的通信区域中时,用户可以在成员上注册位置信息以及用户与成员之间的距离。 版权所有(C)2005,JPO&NCIPI

    Method and device for forming pattern type photoresist layer
    3.
    发明专利
    Method and device for forming pattern type photoresist layer 审中-公开
    形成图案型光电陶瓷层的方法和装置

    公开(公告)号:JP2005252025A

    公开(公告)日:2005-09-15

    申请号:JP2004061127

    申请日:2004-03-04

    CPC classification number: G03F7/70633

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for forming a pattern type photoresist layer capable of shortening a cycle time and a re-processing time in a pattern transfer process. SOLUTION: The forming method of the pattern type photoresist layer matched with a predetermined wafer layer is provided. The photoresist layer is formed on a substrate and exposed. An overlaid offset between the exposed part of the photoresist layer and the predetermined wafer layer is measured to determine whether the exposed part of the photoresist layer matches with the predetermined wafer layer or not. A development stage is effected in the case that the exposed part of the photoresist layer matches with the predetermined wafer layer. A device is also provided for forming the pattern type photoresist layer. This device feedbacks immediately the overlaid offset utilizing the method, whereby the cycle time and the re-processing time in the pattern transfer process are shortened. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 解决的问题:提供一种形成图案型光刻胶层的方法和装置,其能够缩短图案转印处理中的周期时间和重新处理时间。 解决方案:提供了与预定晶片层匹配的图案型光致抗蚀剂层的形成方法。 光致抗蚀剂层形成在基板上并露出。 测量光致抗蚀剂层的暴露部分和预定晶片层之间的重叠偏移,以确定光致抗蚀剂层的露出部分是否与预定晶片层匹配。 在光刻胶层的露出部分与预定的晶片层匹配的情况下,进行显影阶段。 还提供了用于形成图案型光致抗蚀剂层的装置。 该装置利用该方法立即反馈重叠的偏移,从而缩短了图案转印处理中的周期时间和重新处理时间。 版权所有(C)2005,JPO&NCIPI

    Porous low dielectric constant thin film and its manufacturing method
    4.
    发明专利
    Porous low dielectric constant thin film and its manufacturing method 审中-公开
    多孔低介电常数薄膜及其制造方法

    公开(公告)号:JP2007258403A

    公开(公告)日:2007-10-04

    申请号:JP2006080140

    申请日:2006-03-23

    Abstract: PROBLEM TO BE SOLVED: To provide the structure of a porous low dielectric constant material thin film and related manufacturing method for solving various problems associated with the conventional technology.
    SOLUTION: The method of manufacturing the porous low dielectric constant material thin film includes processes of: (a) preparing a substrate; (b) conducting a first chemical vapor deposition (CVD) process, and introducing a backbone precursor into a deposition chamber to form an interfacial dielectric layer on the substrate; (c) conducting a second CVD process, introducing a porogen precursor into the deposition chamber while at the same time introducing a backbone precursor, and combining the porogen precursor with the backbone precursor to form a backbone layer containing porogen on the interfacial dielectric layer; and (d) removing the porogen out of the backbone layer to form an ultralow dielectric constant material layer having a plurality of pores. The interfacial dielectric layer and the ultralow dielectric constant material layer constitute the porous low dielectric constant material thin film.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供多孔低介电常数材料薄膜的结构以及用于解决与传统技术相关的各种问题的相关制造方法。 解决方案:制造多孔低介电常数材料薄膜的方法包括以下工艺:(a)制备衬底; (b)进行第一化学气相沉积(CVD)工艺,并将骨架前体引入沉积室以在衬底上形成界面介电层; (c)进行第二CVD工艺,将致孔剂前体引入沉积室,同时引入骨架前体,并将致孔剂前体与骨架前体组合以在界面介电层上形成含有致孔剂的骨架层; 和(d)从骨架层除去致孔剂以形成具有多个孔的超低介电常数材料层。 界面电介质层和超低介电常数材料层构成多孔低介电常数材料薄膜。 版权所有(C)2008,JPO&INPIT

    Bevel gradient dichroic film for lcos display, lcos display device and its inspecting method
    5.
    发明专利
    Bevel gradient dichroic film for lcos display, lcos display device and its inspecting method 审中-公开
    用于LCOS显示器,LCOS显示器件及其检测方法的水平梯形二层膜

    公开(公告)号:JP2005215636A

    公开(公告)日:2005-08-11

    申请号:JP2004025770

    申请日:2004-02-02

    Abstract: PROBLEM TO BE SOLVED: To provide a bevel gradient dichroic film, used in an off-axis type LCOS (liquid crystal on silicon) display device. SOLUTION: The bevel gradient dichroic film is equipped with a dichroic film having film characteristics, including gradient direction. The gradient direction depends on the incident angle of incident light so as to provide the optical characteristics that the light spots of the incident light on the dichroic film are distributed uniformly. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:提供用于离轴型LCOS(硅液晶)显示装置的斜面梯度二向色膜。

    解决方案:斜面梯度二向色膜配备有具有膜特性的二向色膜,包括梯度方向。 梯度方向取决于入射光的入射角,以提供均匀分布在二向色膜上的入射光的光斑的光学特性。 版权所有(C)2005,JPO&NCIPI

    Rubbing device for liquid crystal display substrate and rubbing method

    公开(公告)号:JP2004212806A

    公开(公告)日:2004-07-29

    申请号:JP2003001443

    申请日:2003-01-07

    CPC classification number: G02F1/133784

    Abstract: PROBLEM TO BE SOLVED: To enhance rubbing performance by decreasing the defects of rubbing and to prolong the lifetime of a roller and to improve the efficiency of rubbing in a rubbing process.
    SOLUTION: The rubbing device further has a conditioning roller, in addition to the rubbing roller, so as to promptly restore the rubbing roller in order to prolong the lifetime of the roller and to improve the efficiency of rubbing in a rubbing process. The rubbing device employs the conditioning roller in addition to the rubbing roller in such a manner, and as a result thereof, the rubbing device eventually newly includes a conditioning process for adjusting the rubbing roller in the rubbing process. The cycle time of manufacturing can be thereby shortened and productivity can be improved.
    COPYRIGHT: (C)2004,JPO&NCIPI

    Integrated circuit with air gaps and its manufacturing method

    公开(公告)号:JP2004172620A

    公开(公告)日:2004-06-17

    申请号:JP2003385281

    申请日:2003-11-14

    Abstract: PROBLEM TO BE SOLVED: To provide a high-performance integrated circuit, particularly an integrated circuit with air gaps that fully supports metal interconnection, for the solution of problems associated with the prior art. SOLUTION: The structure of the integrated circuit comprises: a substrate 11 with an underlayer 12; the first metallic pattern 13 formed in the underlayer; the second metallic layer 17 formed above the first metallic pattern; a supporting structure with an isotropic-etched dielectric layer 14 that supports the second metallic pattern formed between the first metallic pattern and the second metallic pattern; and multiple air gaps 18a formed in a gap in the second metallic pattern that is composed of a capping layer 19. COPYRIGHT: (C)2004,JPO

    Method of manufacturing self-alignment bipolar transistor

    公开(公告)号:JP2004158645A

    公开(公告)日:2004-06-03

    申请号:JP2002322867

    申请日:2002-11-06

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a self-alignment transistor, which can simplify the manufacturing process and reduce costs in the manufacturing process.
    SOLUTION: In the method of manufacturing a self-alignment bipolar transistor on a substrate 200 including an epitaxial layer 202, a first insulating layer 204 and a second insulating layer 206 are sequentially formed, and an opening is formed in the second insulating layer. On the sidewall of this opening, a conductive spacer 210 is formed, and using the second insulating layer and conductive spacer as a mask, the first insulating layer within the opening is removed. Then a conductive layer 212 as an emitter is formed within the opening, and then the second insulating layer is completely removed. This emitter is subjected to doping. Using the emitter and the conductive spacer as a mask, one portion of the first insulating layer is removed, and using the emitter and conductive spacer as a mask, the epitaxial layer is subjected to different doping to change one portion of the layer into a base contact region 218.
    COPYRIGHT: (C)2004,JPO

    METHOD FOR MANUFACTURING INTEGRATED CIRCUIT
    10.
    发明专利

    公开(公告)号:JP2003179140A

    公开(公告)日:2003-06-27

    申请号:JP2002358268

    申请日:2002-12-10

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double-damascene process which exhibits a wide process flexibility and can be easily adapted in mass-production process. SOLUTION: After an etch stop layer 54 is patterned for forming an opening 72 corresponding to a pattern in a connection which is formed on the first level of a two-level connection structure, an intermetallic dielectric layer 58 is provided on it and a photoresist mask 62 is provided on it. Openings 64 and 66 of the mask 62 correspond to the wiring pattern provided on the second level of the connection structure and a dielectric layer 58 is partially exposed from them. The dielectric layer 58 is etched and the etching is advanced in such a way that an opening 68 is produced in the exposed part of the stop layer 54 from the opening 72 of the interlayer dielectric layer 52. In other words, openings for both of the wiring on the second level and the connection on the first level are demarcated by a single etching process. Further, the opening 72 of the stop layer is tapered with its upper diameter being larger than its lower diameter. COPYRIGHT: (C)2003,JPO

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