公开(公告)号：US11744160B2

公开(公告)日：2023-08-29

申请号：US17064606

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

公开(公告)号：US11705498B2

公开(公告)日：2023-07-18

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20220238677A1

公开(公告)日：2022-07-28

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20210391339A1

公开(公告)日：2021-12-16

申请号：US16923117

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/8238

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US10763357B2

公开(公告)日：2020-09-01

申请号：US16828903

申请日：2020-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L23/52 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L27/092 ,  H01L29/778 ,  H01L29/66 ,  H01L27/04 ,  H01L29/24 ,  H01L21/8238 ,  H01L29/16

Abstract: A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.

公开(公告)号：US10312364B2

公开(公告)日：2019-06-04

申请号：US15723186

申请日：2017-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L23/52 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes a first dielectric layer on a substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, a 2D material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer, a gate dielectric layer on the 2D material layer, and a gate electrode on the gate dielectric layer.

公开(公告)号：US10032672B1

公开(公告)日：2018-07-24

申请号：US15666583

申请日：2017-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Shih-Hung Tsai ,  Chorng-Lih Young

IPC: H01L21/82 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a first fin; forming a first set of gate structures on the first fin, where the gate structures are surrounded by an interlayer dielectric; forming a first contact hole in the interlayer dielectric between two adjacent gate structures; forming a first dopant source layer on the bottom of the first contact hole, where the dopant source layer comprise dopants with a first conductivity type; and annealing the first dopant source layer to diffuse the dopants out of the first dopant source layer.

公开(公告)号：US09985123B2

公开(公告)日：2018-05-29

申请号：US15602087

申请日：2017-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US09929134B2

公开(公告)日：2018-03-27

申请号：US14817186

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.

公开(公告)号：US09922882B1

公开(公告)日：2018-03-20

申请号：US15595959

申请日：2017-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yi-Hui Lee

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823475 ,  H01L21/02063 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/768 ,  H01L21/823418 ,  H01L21/823431

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided, and an epitaxial structure is formed on the substrate. A first dielectric layer covering the epitaxial structure and the substrate is formed. A patterned hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the patterned hard mask layer and the first dielectric layer. A patterned photoresist layer is formed on the second dielectric layer. A dry etching process is performed with the pattern hard mask layer and the patterned photoresist layer as masks. The dry etching process forms a contact opening in the first dielectric layer, and the contact opening exposes at least a part of the epitaxial structure. A wet etching process is performed after the dry etching process, and the wet etching process removes the patterned hard mask layer and the second dielectric layer together.