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    Semiconductor structure
    1.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US10600882B2

    公开(公告)日：2020-03-24

    申请号：US14880275

    申请日：2015-10-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

    IPC: H01L21/70 ,  H01L29/49 ,  H01L29/423

    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.

    Semiconductor device and fabrication method thereof
    2.
    发明授权
    Semiconductor device and fabrication method thereof 有权

    公开(公告)号：US10199374B2

    公开(公告)日：2019-02-05

    申请号：US15825057

    申请日：2017-11-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

    IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L49/02

    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

    METHOD FOR FORMING A TWO-LAYERED HARD MASK ON TOP OF A GATE STRUCTURE
    6.
    发明申请
    METHOD FOR FORMING A TWO-LAYERED HARD MASK ON TOP OF A GATE STRUCTURE 有权
    在门顶结构上形成两层硬掩模的方法

    公开(公告)号：US20160315007A1

    公开(公告)日：2016-10-27

    申请号：US15201511

    申请日：2016-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

    IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/308

    CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

    Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 去除栅极结构的一部分; 在第一ILD层和栅极结构上形成第一掩模层; 去除栅极结构上的第一ILD层上的第一掩模层和栅极结构上的第一掩模层的一部分，以在栅极结构上形成第一硬掩模; 在第一ILD层，第一硬掩模和栅极结构上形成第二掩模层; 以及平坦化所述第二掩模层以在所述栅极结构上形成第二硬掩模，其中所述第一硬掩模，所述第二硬掩模和所述第一ILD层的顶表面是共面的。

    Manufacturing method of semiconductor structure for preventing surface of fin structure from damage and providing improved process window
    7.
    发明授权
    Manufacturing method of semiconductor structure for preventing surface of fin structure from damage and providing improved process window 有权
    半导体结构的制造方法，用于防止翅片结构的表面损坏并提供改进的工艺窗口

    公开(公告)号：US09349653B2

    公开(公告)日：2016-05-24

    申请号：US14539225

    申请日：2014-11-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Chih-Sen Huang ,  Li-Wei Feng ,  Jyh-Shyang Jenq

    IPC: H01L21/8228 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/768

    CPC classification number: H01L21/823475 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66795

    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.

    Abstract translation: 提供一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成翅片结构和层间电介质层。 在基板上形成多个栅极结构。 在栅极结构上形成盖层。 在盖层上形成硬掩模。 在硬掩模上形成覆盖栅极结构的第一图案化光致抗蚀剂层。 硬掩模被蚀刻和图案化以形成图案化的硬掩模，使得图案化的硬掩模覆盖栅极结构。 在图案化的硬掩模上形成包括对应于鳍结构的多个开口的第二图案化光致抗蚀剂层。 蚀刻覆盖层和层间电介质层以形成暴露鳍结构的一部分的多个第一沟槽。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
    半导体结构及其工艺

    公开(公告)号：US20160071800A1

    公开(公告)日：2016-03-10

    申请号：US14513230

    申请日：2014-10-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu ,  Hsin-Fu Huang ,  Chun-Yuan Wu ,  Shih-Fang Tzou

    IPC: H01L23/535 ,  H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

    Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。

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