公开(公告)号：US20210242214A1

公开(公告)日：2021-08-05

申请号：US17235950

申请日：2021-04-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108

Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

公开(公告)号：US20210242013A1

公开(公告)日：2021-08-05

申请号：US17234818

申请日：2021-04-20

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033

Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

公开(公告)号：US11038014B2

公开(公告)日：2021-06-15

申请号：US16154704

申请日：2018-10-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Ching Chang ,  Kai-Lou Huang ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L29/76 ,  H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

公开(公告)号：US10971498B2

公开(公告)日：2021-04-06

申请号：US16137513

申请日：2018-09-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ming Lu ,  Fu-Che Lee ,  Feng-Yi Chang

IPC: H01L27/108

Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.

公开(公告)号：US10784265B2

公开(公告)日：2020-09-22

申请号：US16273057

申请日：2019-02-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

Abstract: The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.

公开(公告)号：US20200273862A1

公开(公告)日：2020-08-27

申请号：US16361222

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Han Wu ,  Feng-Yi Chang ,  Fu-Che Lee ,  Wen-Chieh Lu

IPC: H01L27/108

Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.

公开(公告)号：US10672648B2

公开(公告)日：2020-06-02

申请号：US15937849

申请日：2018-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan

IPC: H01L21/768 ,  H01L27/108 ,  H01L21/311

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a tapered sidewall in the second layer and the first layer. After that, the tapered sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.

公开(公告)号：US10672612B2

公开(公告)日：2020-06-02

申请号：US15969788

申请日：2018-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Gang-Yi Lin ,  Feng-Yi Chang ,  Ying-Chih Lin ,  Fu-Che Lee

IPC: H01L21/033 ,  H01L21/311

Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.

公开(公告)号：US10529571B1

公开(公告)日：2020-01-07

申请号：US16262913

申请日：2019-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/3213

Abstract: A method of fabricating a patterned structure includes the following steps. A pattern transfer layer is formed on a material layer. The pattern transfer layer is formed above a first region and a second region. First patterns are formed on the pattern transfer layer. A mask layer is formed. A first part of the mask layer covers the first patterns above the first region. A first cap layer is formed covering the first part of the mask layer and the first patterns above the second region. The first cap layer covering the first part of the mask layer is removed for exposing the first part of the mask layer. The first part of the mask layer is removed. A first etching process is performed to the pattern transfer layer with the first patterns above the first region as a mask after removing the first part of the mask layer.

公开(公告)号：US20190341487A1

公开(公告)日：2019-11-07

申请号：US16509475

申请日：2019-07-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L29/78 ,  H01L27/108 ,  H01L21/02 ,  H01L21/762 ,  H01L21/4757

Abstract: A method of forming a semiconductor structure is disclosed, comprising providing a substrate, forming at least a gate trench extending along a first direction in the substrate, forming a gate dielectric layer conformally covering the gate trench, forming a sacrificial layer on the gate dielectric layer and completely filling the gate trench, forming a plurality of openings through the sacrificial layer in the gate trench thereby exposing a portion of the gate dielectric layer, forming a dielectric material in the openings, performing an etching back process to remove a portion of the dielectric material until the dielectric material only remains at a lower portion of each of the openings thereby obtaining a plurality of intervening structures, removing the sacrificial layer, and forming a gate metal filling the gate trench, wherein the intervening structures are disposed between the gate metal and the gate dielectric layer.