公开(公告)号：US20100244158A1

公开(公告)日：2010-09-30

申请号：US12797404

申请日：2010-06-09

Applicant: Yongjun Jeff Hu ,  Allen McTeer ,  Naga Chandrasekaran

Inventor： Yongjun Jeff Hu ,  Allen McTeer ,  Naga Chandrasekaran

IPC: H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/31654 ,  H01L21/76825 ,  H01L29/78

Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.

Abstract translation: 用于选择性氧化半导体结构的方法包括产生包含氧化源气体的气体团簇离子束，将气体团簇离子束引导到与导电线相邻的衬底的区域，并将该区域暴露于包含氧化物质的气体团簇离子束 。 利用气体簇离子束使得能够以比典型的氧化过程低的温度选择性地氧化目标区域，从而减少或消除导电线的氧化。 还公开了包括使用这种方法形成的晶体管的半导体器件。

公开(公告)号：US07749849B2

公开(公告)日：2010-07-06

申请号：US11958972

申请日：2007-12-18

Applicant: Yongjun Jeff Hu ,  Allen McTeer ,  Naga Chandrasekaran

Inventor： Yongjun Jeff Hu ,  Allen McTeer ,  Naga Chandrasekaran

IPC: H01L21/336

CPC classification number: H01L21/28247 ,  H01L21/31654 ,  H01L21/76825 ,  H01L29/78

Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.

Abstract translation: 用于选择性氧化半导体结构的方法包括产生包含氧化源气体的气体团簇离子束，将气体团簇离子束引导到与导电线相邻的衬底的区域，并将该区域暴露于包含氧化物质的气体团簇离子束 。 利用气体簇离子束使得能够以比典型的氧化过程低的温度选择性地氧化目标区域，从而减少或消除导电线的氧化。 还公开了包括使用这种方法形成的晶体管的半导体器件。

公开(公告)号：US20090152629A1

公开(公告)日：2009-06-18

申请号：US11958972

申请日：2007-12-18

Applicant: Yongjun Jeff Hu ,  Allen McTeer ,  Naga Chandrasekaran

Inventor： Yongjun Jeff Hu ,  Allen McTeer ,  Naga Chandrasekaran

IPC: H01L21/469 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/31654 ,  H01L21/76825 ,  H01L29/78

Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.

Abstract translation: 用于选择性氧化半导体结构的方法包括产生包含氧化源气体的气体团簇离子束，将气体团簇离子束引导到与导电线相邻的衬底的区域，并将该区域暴露于包含氧化物质的气体团簇离子束 。 利用气体簇离子束使得能够以比典型的氧化过程低的温度选择性地氧化目标区域，从而减少或消除导电线的氧化。 还公开了包括使用这种方法形成的晶体管的半导体器件。

公开(公告)号：US07109115B2

公开(公告)日：2006-09-19

申请号：US11071922

申请日：2005-03-04

Applicant: Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

Inventor： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

Abstract translation: 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

公开(公告)号：US07064390B2

公开(公告)日：2006-06-20

申请号：US11012049

申请日：2004-12-14

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L27/12

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract translation: 一种半导体器件，例如CMOS器件，其在PMOS区域中具有高功函数的栅极和NMOS区域中的低功函数及其制造方法。 使用氮注入或等离子体退火，低功函数W（或Co x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x 形成在NMOS区域中，同时形成高功函数W（或CoSi x Sb）/ Ta 5 Si 3 / GO x / Si栅叠层 在PMOS区域。 改进的方法也不需要已知降解g（跨导）性能的氮化的GOx。 半导体器件的材料表现出对相邻材料的改善的粘附特性和低内应力。

公开(公告)号：US07038318B2

公开(公告)日：2006-05-02

申请号：US10689894

申请日：2003-10-21

Applicant: Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

Inventor： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

IPC: H01L29/40

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

公开(公告)号：US06774022B2

公开(公告)日：2004-08-10

申请号：US10629199

申请日：2003-07-29

Applicant: Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

Inventor： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L213205

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract translation: 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 通常，钝化层包括SixOyNz。

公开(公告)号：US06743720B2

公开(公告)日：2004-06-01

申请号：US10405351

申请日：2003-04-01

Applicant: Gary Chen ,  Li Li ,  Yongjun Jeff Hu

Inventor： Gary Chen ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L21465

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32134

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract translation: 金属氮化物和金属氮氧化物挤出物通常在金属硅化物上形成。 这些挤压可能导致短路并降低加工产量。 本发明公开了一种选择性地去除这种挤出物的方法。 在一个实施方案中，包含氧化剂和螯合剂的新型湿蚀刻选择性地从存储器阵列中的字线除去挤出物。 在另一个实施方案中，湿蚀刻包括调节蚀刻的pH以选择性地相对于字线中的其它物质去除某些挤出物的碱。 因此，可以使用新的金属硅化物结构来形成新颖的字线和其他类型的集成电路。

公开(公告)号：US06683357B2

公开(公告)日：2004-01-27

申请号：US10280463

申请日：2002-10-25

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L2976

CPC classification number: H01L21/76879 ,  H01L21/28518

Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal suicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.

Abstract translation: 本发明包括形成半导体结构的方法。 在含硅基板上形成富金属的硅化物层，在富金属的硅化物层上形成金属氮化物层。 将富金属的金属硅化物层和金属氮化物层热处理以将一些富金属的金属硅化物转化成化学计量的金属硅化物区域。 热处理还将氮从金属氮化物层驱动到富金属的金属硅化物层中，以将一些富金属的金属硅化物层转化为包含金属，硅和氮的区域。 本发明还包括包含MSi2层和MSiqNr层的半导体结构，其中M是Ta，W或Mo，并且q和r都大于0且小于2。

公开(公告)号：US06645798B2

公开(公告)日：2003-11-11

申请号：US09887449

申请日：2001-06-22

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L21336

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.