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    Source-channel interaction in 3D circuit
    1.
    发明授权
    Source-channel interaction in 3D circuit 有权
    3D电路中的源通道交互

    公开(公告)号：US09299767B1

    公开(公告)日：2016-03-29

    申请号：US14498640

    申请日：2014-09-26

    Applicant: John Mark Meldrim ,  Yushi Hu ,  Yongjun Jeff Hu ,  Everett Allen McTeer

    Inventor： John Mark Meldrim ,  Yushi Hu ,  Yongjun Jeff Hu ,  Everett Allen McTeer

    IPC: H01L29/04 ,  H01L27/115 ,  H01L27/105

    CPC classification number: H01L27/0688 ,  H01L29/7827

    Abstract: A multilayer source provides charge carriers to a multitier channel connector. The source includes a metal silicide layer on a substrate and a metal nitride layer between the metal silicide layer and the channel. The metal silicide and the metal nitride are processed without an intervening oxide layer between them. In one embodiment, the source further includes a silicon layer between the metal nitride layer and the channel. The silicon layer can also be processed without an intervening oxide layer. Thus, the source does not have an intervening oxide layer from the substrate to the channel.

    Abstract translation: 多层光源将电荷载体提供给多层通道连接器。 源包括衬底上的金属硅化物层和金属硅化物层和沟道之间的金属氮化物层。 金属硅化物和金属氮化物在它们之间没有中间的氧化物层被加工。 在一个实施例中，源还包括在金属氮化物层和沟道之间的硅层。 硅层也可以在没有中间氧化物层的情况下被加工。 因此，源不具有从衬底到通道的中间氧化物层。

    Methods of fabricating a transistor gate including cobalt silicide
    2.
    发明授权
    Methods of fabricating a transistor gate including cobalt silicide 有权
    制造包括硅化钴的晶体管栅极的方法

    公开(公告)号：US08652912B2

    公开(公告)日：2014-02-18

    申请号：US11636192

    申请日：2006-12-08

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/336

    CPC classification number: H01L29/4975 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10891 ,  H01L27/115 ,  H01L27/11521

    Abstract: A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed.

    Abstract translation: 一种制造具有包括硅化钴的导电元件的晶体管栅极的方法包括使用牺牲材料作为晶体管栅极的侧壁间隔物之间​​的位置保持器，直到高温处理（例如升高的源极和漏极区域的制造） 已经完成 此外，还公开了具有在其导电元件中包括硅化钴的晶体管栅极的半导体器件（例如，DRAM器件和NAND闪存器件），晶体管的晶体管具有在其晶体管栅极中具有升高的源极和漏极区域以及硅化钴的晶体管。 还公开了包括具有牺牲材料的晶体管栅极或侧壁间隔物的上部之间的间隙的中间半导体器件结构。

    Methods Of Forming Transistor Gates
    4.
    发明申请
    Methods Of Forming Transistor Gates 有权
    形成晶体管门的方法

    公开(公告)号：US20130012013A1

    公开(公告)日：2013-01-10

    申请号：US13605848

    申请日：2012-09-06

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/283

    CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中公共处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

    Semiconductor Processing Methods, And Methods Of Forming Isolation Structures
    5.
    发明申请
    Semiconductor Processing Methods, And Methods Of Forming Isolation Structures 有权
    半导体加工方法和形成隔离结构的方法

    公开(公告)号：US20120329231A1

    公开(公告)日：2012-12-27

    申请号：US13603100

    申请日：2012-09-04

    Applicant: Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    Inventor： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    IPC: H01L21/762 ,  H01L21/336

    CPC classification number: H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    Abstract translation: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

    Semiconductor constructions for transistor gates and NAND cell units
    6.
    发明授权
    Semiconductor constructions for transistor gates and NAND cell units 有权
    晶体管栅极和NAND单元的半导体结构

    公开(公告)号：US08288817B2

    公开(公告)日：2012-10-16

    申请号：US12986487

    申请日：2011-01-07

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中公共处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

    Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts
    9.
    发明申请
    Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts 有权
    形成CoSi2的方法，形成场效应晶体管的方法和形成导电触点的方法

    公开(公告)号：US20090035938A1

    公开(公告)日：2009-02-05

    申请号：US12244692

    申请日：2008-10-02

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/44

    CPC classification number: H01L29/665 ,  H01L21/28518

    Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

    Abstract translation: 本发明包括形成CoSi 2的方法，形成场效应晶体管的方法以及形成导电触点的方法。 在一个实施方案中，形成CoSi 2的方法包括在含硅衬底上形成包含MSix的基本非晶层，其中“M”至少包括除钴以外的一些金属。 包含钴的层沉积在基本上无定形的含MSix的层上。 将衬底退火有效地将含钴层的钴扩散通过基本上无定形的含MSix层并与含硅衬底的硅结合，以在基本上无定形的含MSix层下形成CoSi 2。 考虑了其他方面和实现。

    Metal gate engineering for surface P-channel devices
    10.
    发明授权
    Metal gate engineering for surface P-channel devices 有权
    金属门工程用于表面P沟道器件

    公开(公告)号：US07368796B2

    公开(公告)日：2008-05-06

    申请号：US11371657

    申请日：2006-03-08

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L31/00

    CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975

    Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

    Abstract translation: 一种半导体器件，例如CMOS器件，其在PMOS区域中具有高功函数的栅极和NMOS区域中的低功函数及其制造方法。 使用氮注入或等离子体退火，低功函数W（或Co x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x Si x 形成在NMOS区域中，同时形成高功函数W（或CoSi x Sb）/ Ta 5 Si 3 / GO x / Si栅叠层 在PMOS区域。 改进的方法也不需要已知降解g（跨导）性能的氮化的GOx。 半导体器件的材料表现出对相邻材料的改善的粘附特性和低内应力。

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