公开(公告)号：US09568933B2

公开(公告)日：2017-02-14

申请号：US14020949

申请日：2013-09-09

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Ansgar Pottbaecker ,  Panny Cai

IPC: G05F3/16 ,  G05F3/08 ,  G05F3/30 ,  G05F3/22

CPC classification number: G05F3/08 ,  G05F3/22 ,  G05F3/30

Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract translation: 带隙参考电压发生器包括具有第一电阻器，第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。

公开(公告)号：US12253562B2

公开(公告)日：2025-03-18

申请号：US18186624

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F1/24 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/14

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

公开(公告)号：US12066962B2

公开(公告)日：2024-08-20

申请号：US18309103

申请日：2023-04-28

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G05B19/042 ,  G06F9/54 ,  G06F11/07 ,  G06F11/10 ,  G06F13/40 ,  G06F13/42 ,  H04L12/40 ,  H04L12/403 ,  H03M13/09

CPC classification number: G06F13/362 ,  G05B19/042 ,  G06F9/542 ,  G06F11/0739 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1004 ,  G06F13/4068 ,  G06F13/4282 ,  H04L12/40006 ,  H04L12/40013 ,  H04L12/40078 ,  H04L12/403 ,  G05B2219/1215 ,  G05B2219/2231 ,  G05B2219/31179 ,  H03M13/09 ,  H04L2012/40215

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US11914499B2

公开(公告)日：2024-02-27

申请号：US17515212

申请日：2021-10-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant ,  Misaele Marletti ,  Alessandro Daolio

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3082 ,  G06F11/3466

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

公开(公告)号：US20240048405A1

公开(公告)日：2024-02-08

申请号：US18489590

申请日：2023-10-18

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics Design & Application S.R.O.

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/423 ,  H04L12/40169 ,  H04L2012/40215

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US20240048404A1

公开(公告)日：2024-02-08

申请号：US18350345

申请日：2023-07-11

Applicant: STMicroelectronics Application GMBH

Inventor： Fred Rennig

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/40215

Abstract: An electronic device includes a CAN protocol controller, a first communication port configured to be coupled to a first segment of a differential bus, and a second communication port configured to be coupled to a second segment of the differential bus. A first CAN transceiver circuit is coupled to the CAN protocol controller and is configured to receive a first CAN transmission signal and to transmit a first CAN reception signal. The first CAN transceiver is configured to drive a differential voltage at the first segment of the differential bus based on the first CAN transmission signal and to sense a differential voltage at the first segment of the differential bus. The second communication port is enabled in response to a control signal being de-asserted and disabled in response to the control signal being asserted.

公开(公告)号：US11824681B2

公开(公告)日：2023-11-21

申请号：US17814113

申请日：2022-07-21

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/423 ,  H04L12/40169 ,  H04L2012/40215

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US11810911B2

公开(公告)日：2023-11-07

申请号：US16897205

申请日：2020-06-09

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (TOURS) SAS

Inventor： Mathieu Rouviere ,  Arnaud Yvon ,  Mohamed Saadna ,  Vladimir Scarpa

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/0254 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

公开(公告)号：US11762794B2

公开(公告)日：2023-09-19

申请号：US17747800

申请日：2022-05-18

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger ,  Roberto Colombo

IPC: G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F13/42 ,  G06F21/60 ,  G06F21/72

CPC classification number: G06F13/28 ,  G06F9/30105 ,  G06F9/3877 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/72

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

公开(公告)号：US20230269150A1

公开(公告)日：2023-08-24

申请号：US18309397

申请日：2023-04-28

Applicant: STMicroelectronics Application GMBH

Inventor： Fred Rennig

IPC: H04L43/08

CPC classification number: H04L43/08 ,  H04L12/40

Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.