PROCESSOR BRIDGE WITH DISSIMILAR DATA ACCESS
    96.
    发明申请
    PROCESSOR BRIDGE WITH DISSIMILAR DATA ACCESS 审中-公开
    处理器桥与数据访问

    公开(公告)号:WO99066405A1

    公开(公告)日:1999-12-23

    申请号:PCT/US1999/012432

    申请日:1999-06-03

    Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode. In a subsequent phase the bridge control mechanism responds to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processing sets. In this manner the data from one processing set can be copied to the other processing set while in a combined mode.

    Abstract translation: 用于多处理器系统的桥接器包括用于连接到第一处理集合的I / O总线,第二处理集合的I / O总线和设备总线的总线接口。 桥接控制机制可操作以比较第一和第二处理集合的I / O访问的地址和数据相位。 直接存储器访问机制可操作以启动直接存储器访问操作,以将每个处理器集合中的相应位置读取为与每个处理集相关联的相应不同数据寄存器。 桥接控制机制在直接存储器访问操作期间可操作以忽略不同数据写访问的数据阶段的差异。 因此,可以以组合(锁步比较)模式将不同的数据从处理器传输到桥中。 在随后的阶段中,桥接控制机制响应由第一和第二处理集合共同提供的用于不同数据读取访问的读取目的地地址,以将从所确定的一个不同数据寄存器读取的数据提供给第一和第二处理集 。 以这种方式,来自一个处理集合的数据可以在组合模式下被复制到另一个处理集合。

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