公开(公告)号：US08154307B2

公开(公告)日：2012-04-10

申请号：US12233421

申请日：2008-09-18

Applicant: Andrea Cathelin ,  Sylvain Godet ,  Olivier Llopis ,  Éric Tournier ,  Stephane Thuries

Inventor： Andrea Cathelin ,  Sylvain Godet ,  Olivier Llopis ,  Éric Tournier ,  Stephane Thuries

IPC: G01R29/26 ,  G01R23/20

CPC classification number: G01R31/31709

Abstract: An electronic circuit includes several (at least two) oscillating and/or resonant devices. The circuit uses a measuring device to measure the phase noise of one of the two oscillating/resonant devices. This measuring device is integrated on a chip on which the oscillating/resonant device to be measured is also integrated. The circuits and methods described find application in the area of radiofrequency/high frequency electronics RF/HF, in particular adapted to general public applications in mobile communication systems and/or to metrology.

Abstract translation: 电子电路包括几个（至少两个）振荡和/或谐振装置。 该电路使用测量装置来测量两个振荡/谐振装置之一的相位噪声。 该测量装置集成在芯片上，待测量的振荡/谐振装置也被集成在芯片上。 所描述的电路和方法可应用于射频/高频电子RF / HF领域，特别适用于移动通信系统中的一般公共应用和/或计量学。

公开(公告)号：US08139823B2

公开(公告)日：2012-03-20

申请号：US13044385

申请日：2011-03-09

Applicant: Fabrice Gensolen ,  Lionel Martin ,  Guy Cathebras

Inventor： Fabrice Gensolen ,  Lionel Martin ,  Guy Cathebras

IPC: G06K9/00 ,  H04N5/228 ,  H04N5/33

CPC classification number: G06T7/20 ,  H04N5/23248 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23264

Abstract: A method for capturing a sequence of video images, using an imager including an estimation of the parameters of a model of global motion between successive images. The method may include measurement of local motions on edges of the images, with the estimation of the parameters of the global motion model performed using the result of the measurement of local motions on the edges of the images.

Abstract translation: 一种使用包括对连续图像之间的全局运动模型的参数的估计的成像器捕获视频图像序列的方法。 该方法可以包括使用图像边缘上的局部运动的测量结果来对全局运动模型的参数的估计来估计图像边缘上的局部运动。

公开(公告)号：US20120042292A1

公开(公告)日：2012-02-16

申请号：US12853627

申请日：2010-08-10

Applicant: Fady Abouzeid ,  Sylvain Clerc ,  Fabian Firmin

Inventor： Fady Abouzeid ,  Sylvain Clerc ,  Fabian Firmin

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors.

Abstract translation: 一种合成耦合在第一和第二电源电压之间并具有多个输入和输出的至少一个逻辑器件的方法，所述逻辑器件包括具有标准栅极长度的多个晶体管，所述方法包括：在at 至少一个逻辑器件，连接在第一或第二电源电压与输出节点之间的一个或多个晶体管; 以及增加所识别的一个或多个晶体管中的每一个的栅极长度。

公开(公告)号：US08102997B2

公开(公告)日：2012-01-24

申请号：US11547195

申请日：2004-03-29

Applicant: Yannick Teglia ,  Fabrice Romain ,  Pierre-Yvan Liardet ,  Pasqualina Fragneto ,  Fabio Sozzani ,  Guido Bertoni

Inventor： Yannick Teglia ,  Fabrice Romain ,  Pierre-Yvan Liardet ,  Pasqualina Fragneto ,  Fabio Sozzani ,  Guido Bertoni

IPC: H04L9/28 ,  H04K1/00

CPC classification number: H04L9/0631 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/122

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

Abstract translation: 一种用于执行Rijndeal算法的处理器，该Rijndeal算法将多个加密回合应用于数据块阵列，以便获得相同大小的阵列，每轮涉及密钥块阵列和数据块替换表，其中所述处理器包括：第一 输入寄存器（102），其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器（111）; 包含密钥块列或中间数据块的第二输入寄存器（101）; 块替换元件（104）在第一寄存器中的选择（103）之后的时间接收数据一个块，并为每个块提供一列块; 向替代电路列块施加循环置换的元件（109）; 以及将置换电路列块与第二寄存器的内容组合的异或组合元件（110），所述组合的结果被加载到输出寄存器中。

公开(公告)号：US20120006980A1

公开(公告)日：2012-01-12

申请号：US13241111

申请日：2011-09-22

Applicant: JÉRÔME ALIEU ,  SIMON GUILLAUMET ,  CHRISTOPHE LEGENDRE ,  HUGHES LEININGER ,  JEAN-PIERRE ODDOU ,  MARC VINCENT

Inventor： JÉRÔME ALIEU ,  SIMON GUILLAUMET ,  CHRISTOPHE LEGENDRE ,  HUGHES LEININGER ,  JEAN-PIERRE ODDOU ,  MARC VINCENT

IPC: H01J3/14 ,  H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/14632

Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.

Abstract translation: 一种制造感光集成电路的方法，包括制造电路控制晶体管，在控制晶体管之上以及在至少一个上电极和至少一个下电极，至少一个光电二极管之间，通过非晶硅层产生入射电磁波的光子 辐射被吸收，在下电极和控制晶体管之间产生至少一个钝化层，并且在控制晶体管和集成电路的外表面之间产生能够反射未被非晶硅层吸收的光子的反射层 。

公开(公告)号：US08063729B2

公开(公告)日：2011-11-22

申请号：US12874609

申请日：2010-09-02

Applicant: Hilal Ezzeddine

Inventor： Hilal Ezzeddine

IPC: H01F5/00

CPC classification number: H03H7/42 ,  H01F19/04 ,  H01P5/10 ,  H03H7/175

Abstract: A mode-switching transformer comprising a first line in common mode and a second line in differential mode, each line comprising two sections in series respectively coupled with one of the two sections of the other line and all sections having the same lengths, the common mode line being connected in series with a capacitor, to lower the central frequency of the transformer passband, the λ/4 lengths of the sections being chosen to correspond to a central frequency greater than the central frequency desired for the transformer.

Abstract translation: 一种模式切换变压器，包括共模中的第一线和差分模式的第二线，每条线包括串联的两个部分，分别与另一条线的两个部分中的一个相连，所有部分具有相同的长度，共模 线路与电容器串联连接，以降低变压器通带的中心频率，选择这些部分的λ/ 4长度对应于大于变压器所需中心频率的中心频率。

公开(公告)号：US08054930B2

公开(公告)日：2011-11-08

申请号：US10841705

申请日：2004-05-07

Applicant: Jean-Pierre Lagarde

Inventor： Jean-Pierre Lagarde

IPC: H03D3/24

CPC classification number: H03L7/0994

Abstract: A circuit is provided for clock recovery. The circuit includes a reference extraction unit for extracting from a datastream time references defining a reference time base, and a digital Phase Locked Loop including a first programmable counter in the guise of a digitally controlled oscillator for overseeing an output time base, a second programmable counter in the guise of a loop divider for overseeing a loop time base, and a dedicated processor capable of executing a program including a first software module in the guise of a phase comparator for comparing values of the loop and reference time bases and generating a loop error, and a second software module in the guise of a loop filter for producing an adaptation value of an increment value of the first programmable counter from the loop error. Also provided are a user terminal and a method for clock recovery.

Abstract translation: 提供电路用于时钟恢复。 该电路包括：参考提取单元，用于从数据流中提取定义参考时基的参考时间;以及数字锁相环，包括用于监视输出时基的数字控制振荡器的伪装的第一可编程计数器，第二可编程计数器 用于监视循环时基的循环分配器的伪装，以及能够执行包括第一软件模块的程序的专用处理器，该第一软件模块用于比较循环和参考时基的值，并产生循环误差 以及环路滤波器的伪装的第二软件模块，用于从循环误差产生第一可编程计数器的增量值的自适应值。 还提供了用于时钟恢复的用户终端和方法。

公开(公告)号：US08045712B2

公开(公告)日：2011-10-25

申请号：US11175915

申请日：2005-07-06

Applicant: Joan Daemen ,  Pierre Guillemin ,  Claude Anguille ,  Michel Bardouillet ,  Pierre-Yvan Liardet ,  Yannick Teglia

Inventor： Joan Daemen ,  Pierre Guillemin ,  Claude Anguille ,  Michel Bardouillet ,  Pierre-Yvan Liardet ,  Yannick Teglia

IPC: H04L9/00

CPC classification number: G06F12/1408 ,  H04L9/065 ,  H04L2209/12

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract translation: 一种由存储在存储器中的数据的集成处理器进行加密的方法和元件，包括应用作为集成电路特有的密钥和初始化向量的函数的加密算法，以及至少记忆密码 数据，初始化向量至少取决于存储器中数据的存储地址。

公开(公告)号：US08044892B2

公开(公告)日：2011-10-25

申请号：US11294991

申请日：2005-12-06

Applicant: Danika Chaussy ,  Céline Mas

Inventor： Danika Chaussy ,  Céline Mas

IPC: G09G3/30

CPC classification number: G09G3/3216 ,  G09G3/3283 ,  G09G2310/0251 ,  G09G2320/0233 ,  G09G2320/043 ,  G09G2330/021

Abstract: A circuit for controlling a matrix display formed of light-emitting diodes, capable of successively selecting lines of the screen and, for each line from a set of selected lines, of selecting columns, the voltage of each selected column settling at an operating voltage. The circuit is capable, before selection of each line from said set of lines, of precharging at least the columns to be selected to a precharge voltage. The circuit includes a device for adjusting the precharge voltage including a measurement circuit capable, on each selection of a line from said set of lines, of measuring the maximum operating voltage from among the operating voltages of the selected columns; a circuit capable of storing the maximum measured operating voltage; and a circuit capable of adjusting the precharge voltage based on the maximum stored operating voltage.

Abstract translation: 一种用于控制由发光二极管形成的矩阵显示的电路，其能够连续地选择屏幕线，并且对于来自一组选定行的每行，选择列，以每个选定列的电压在工作电压下稳定。 在从所述线路组中选择每条线路之前，电路能够至少将要选择的列预先充电到预充电电压。 该电路包括用于调整预充电电压的装置，该装置包括测量电路，该测量电路能够从所述一组线路中选择一条线路，从所选列的工作电压中测量最大工作电压; 能够存储最大测量工作电压的电路; 以及能够基于最大存储的工作电压来调节预充电电压的电路。

公开(公告)号：US20110227194A1

公开(公告)日：2011-09-22

申请号：US13052262

申请日：2011-03-21

Applicant: Simon Jeannot ,  Pascal Tannhof

Inventor： Simon Jeannot ,  Pascal Tannhof

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

Abstract translation: 一种用于在包括一系列金属水平和通孔级别的互连堆叠的金属层中形成电容结构的方法，包括以下步骤：在金属层面形成至少一个其中限定沟槽的导电轨道; 在结构上保形地形成绝缘层; 在沟槽中形成导电材料; 并平坦化结构。