-
公开(公告)号：US20230171969A1
公开(公告)日：2023-06-01
申请号：US17827799
申请日：2022-05-30
Inventor： Xiaoguang WANG , Huihui LI , Wei CHANG , Kanyu CAO
IPC: H01L27/105
CPC classification number: H01L27/1052
Abstract: Embodiment provides a semiconductor structure and a fabrication method thereof, and relates to the field of semiconductor technology. The fabrication method includes providing a substrate including a peripheral circuit region and an array region having a memory cell, where the peripheral circuit region includes a first region and a second region. In the present disclosure, a logic device configured to control the memory cell and a magnetic memory device are simultaneously fabricated in the peripheral circuit region by means of a process for fabricating a dynamic random access memory (DRAM), such that the same semiconductor structure has two types of memory structures at the same time. Compared with a technology for fabricating two types of memory structures separately, fabricating steps can be simplified, and fabricating costs can be reduced.
-
公开(公告)号：US20230171947A1
公开(公告)日：2023-06-01
申请号：US18054994
申请日：2022-11-14
IPC: H01L27/108 , H01L49/02
CPC classification number: H01L27/10811 , H01L27/1085 , H01L28/87 , H01L28/91
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: forming a capacitor on a substrate, where a first support layer is provided between parts of the first electrodes in the capacitor away from the substrate; removing part of a second electrode and part of a first dielectric layer to expose a surface of the first support layer away from the substrate; forming, on the surface of the first support layer away from the substrate, a second support layer having a first hole structure; forming, on a side surface of the first hole structure, a third electrode in contact with the first electrode; forming a second dielectric layer covering the third electrode and being in contact with the first dielectric layer; and forming, on a side surface of the second dielectric layer, a fourth electrode in contact with the second electrode.
-
公开(公告)号：US20230170416A1
公开(公告)日：2023-06-01
申请号：US17817412
申请日：2022-08-04
Inventor： Deyuan XIAO , Yong YU , Guangsu SHAO
IPC: H01L29/78 , H01L29/423 , H01L29/417 , H01L29/66 , H01L29/40 , H01L27/108
CPC classification number: H01L29/7827 , H01L27/108 , H01L29/401 , H01L29/41741 , H01L29/42376 , H01L29/42392 , H01L29/66666
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; preprocessing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.
-
Patent Agency Ranking
公开(公告)号：US20230168636A1
公开(公告)日：2023-06-01
申请号：US17554932
申请日：2021-12-17
Inventor： Leibo LIU , Xiangyu KONG , Jianfeng ZHU , Shouyi YIN , Shaojun WEI
IPC: G05B9/03
CPC classification number: G05B9/03
Abstract: A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.
-
公开(公告)号：US20230094859A1
公开(公告)日：2023-03-30
申请号：US17808797
申请日：2022-06-24
Inventor： Xiaoguang WANG , DINGGUI ZENG , Huihui LI , Jiefang DENG , Kanyu CAO
IPC: H01L23/528 , H01L27/11502 , H01L27/22 , H01L27/24
Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, having a first surface; a plurality of memory cells, located on the first surface of the substrate and arranged according to a first preset pattern; and a plurality of memory contact structures, corresponding to the memory cells in a one-to-one manner, where bottom portions of the memory contact structures are in contact with top portions of the memory cells, and top portions of the memory contact structures are arranged according to a second preset pattern. The bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.
-
106.发明申请公开(公告)号：US20230063767A1
公开(公告)日：2023-03-02
申请号：US17842937
申请日：2022-06-17
Inventor： Kanyu CAO , Xiaoguang WANG , Huihui LI , Dinggui ZENG , Jiefang DENG
Abstract: A method for manufacturing a semiconductor structure, a semiconductor structure and a semiconductor memory are provided. The method includes: providing a substrate; forming an MTJ structure and a first mask structure sequentially on the substrate; patterning the first mask structure to form a first pattern extending in a first direction; forming a second mask structure on the first pattern; patterning the second mask structure to form a second pattern extending in a second direction, in which the first direction intersects the second direction, and is not perpendicular to the second direction; patterning the first pattern by utilizing the second pattern to form a cellular pattern; and transferring the cellular pattern to the MTJ structure to form a cellular MTJ array.
-
公开(公告)号：US20230061921A1
公开(公告)日：2023-03-02
申请号：US17664236
申请日：2022-05-20
Inventor： Guangsu Shao , Weiping Bai , Deyuan Xiao , Yunsong Qiu
IPC: H01L27/108
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps.
-
公开(公告)号：US20230059600A1
公开(公告)日：2023-02-23
申请号：US17836315
申请日：2022-06-09
Inventor： Guangsu Shao , Deyuan Xiao , Yunsong Qiu
IPC: H01L27/108
Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes: forming a plurality of first trenches extending in a first direction on the substrate; forming a plurality of second trenches extending in a second direction on the substrate on which the first trenches are formed; forming a first isolation layer in at least one of the first trenches and at least one of the second trenches, in which o first gaps are respectively provided between the first isolation layer and sidewalls on both sides of the first trench; forming two bit lines which are parallel to each other and extend in the first direction by depositing conductive layers of a first conductive material at bottoms of the first gaps on both sides of the first trench; and forming word lines extending in the second direction above the conductive layers in the first trench and the second trench.
-
-
-
-
-
-
-
Search Results
108
records
(took 0.035 seconds)
