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    SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR
    1.
    发明公开
    SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR 审中-公开

    公开(公告)号：EP4163959A1

    公开(公告)日：2023-04-12

    申请号：EP22765734.3

    申请日：2022-03-02

    Applicant: Changxin Memory Technologies, Inc. ,  Beijing Superstring Academy of Memory Technology

    Inventor： SHAO, Guangsu ,  XIAO, Deyuan ,  BAI, Weiping ,  QIU, Yunsong

    IPC: H01L21/8242

    Abstract: A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, in which the first shallow trench isolation structures isolate a plurality of active areas extending in a first direction in the substrate, and a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer which are stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in a second direction, and the second direction intersects with the first direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in the first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
    2.
    发明公开
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR 审中-公开

    公开(公告)号：EP4160662A1

    公开(公告)日：2023-04-05

    申请号：EP21923590.0

    申请日：2021-11-08

    Applicant: Changxin Memory Technologies, Inc. ,  Beijing Superstring Academy of Memory Technology

    Inventor： SHAO, Guangsu ,  XIAO, Deyuan ,  QIU, Yunsong

    IPC: H01L21/768 ,  H01L27/105

    Abstract: Embodiments of the disclosure provide a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: forming a plurality of first trenches extending in a first direction on the substrate; forming a plurality of second trenches extending in a second direction on the substrate on which the first trenches are formed, in which the first direction is perpendicular to the second direction, and a first depth of the first trenches is greater than a second depth of the second trenches; forming a first isolation layer in each of the first trenches and the second trenches, in which on a section along the second direction, first gaps are respectively provided between the first isolation layer and sidewalls on both sides of each of the first trenches, and a depth of the first gaps is less than the first depth; forming two bit lines which are parallel to each other and extend in the first direction by depositing conductive layers of a first conductive material at bottoms of the first gaps on both sides of each of the first trenches; and forming word lines extending in the second direction above the conductive layers in the first trenches and the second trenches.

    3D STACKED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC EQUIPMENT
    4.
    发明申请
    3D STACKED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC EQUIPMENT 有权

    公开(公告)号：US20250048615A1

    公开(公告)日：2025-02-06

    申请号：US18692912

    申请日：2023-06-08

    Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Xuezheng Ai ,  Xiangsheng Wang ,  Guilei Wang ,  Jin Dai ,  Chao Zhao ,  Wenhua Gui

    IPC: H10B12/00

    Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

    Method for forming capacitor, capacitor and semiconductor device
    7.
    发明授权
    Method for forming capacitor, capacitor and semiconductor device 有权

    公开(公告)号：US12041763B2

    公开(公告)日：2024-07-16

    申请号：US17848895

    申请日：2022-06-24

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Guangsu Shao ,  Mengkang Yu ,  Xingsong Su

    IPC: H01L27/108 ,  H10B12/00

    CPC classification number: H10B12/033 ,  H10B12/31

    Abstract: A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.

    Memory cell, 3D memory and preparation method therefor, and electronic device
    10.
    发明授权
    Memory cell, 3D memory and preparation method therefor, and electronic device 有权

    公开(公告)号：US11825642B1

    公开(公告)日：2023-11-21

    申请号：US18312389

    申请日：2023-05-04

    Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Jin Dai ,  Yong Yu ,  Jing Liang

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.

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