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    MOBILE USER INTERFACE SYSTEM AND METHODS THEREFOR
    101.
    发明申请
    MOBILE USER INTERFACE SYSTEM AND METHODS THEREFOR 审中-公开
    移动用户界面系统及其方法

    公开(公告)号：US20160182501A1

    公开(公告)日：2016-06-23

    申请号：US14579705

    申请日：2014-12-22

    Applicant: ELBIT SYSTEMS OF AMERICA, LLC

    Inventor： Robert A. Woodward ,  Daniel M. Herring ,  Andrew W. Hull

    IPC: H04L29/06 ,  G06K9/00 ,  G06F12/14 ,  G06T1/60

    CPC classification number: H04L63/0861 ,  G06F12/1408 ,  G06F21/78 ,  G06K9/00087 ,  G06K9/00617 ,  G06T1/20 ,  H04L63/0435

    Abstract: A system. At least some embodiments are a system including a first processor and a non-volatile random access memory coupled to the first processor, the non-volatile random access memory storing program instructions for execution by the first processor in which the programming instructions are stored only in encrypted form. The system further includes an encryption engine coupled to the first processor and coupled to the non-volatile random access memory. A bridge logic device coupled is to the processor and configured to couple to an external peripheral network bus. The encryption engine is configured to decrypt software program instructions stored in the non-volatile random access memory for execution by the first processor.

    Abstract translation: 一个系统。 至少一些实施例是包括耦合到第一处理器的第一处理器和非易失性随机存取存储器的系统，非易失性随机存取存储器存储用于由第一处理器执行的程序指令，其中编程指令仅存储在 加密形式。 该系统还包括耦合到第一处理器并耦合到非易失性随机存取存储器的加密引擎。 耦合到该处理器并被配置为耦合到外部外围网络总线的桥逻辑器件。 加密引擎被配置为解密存储在非易失性随机存取存储器中的软件程序指令，以供第一处理器执行。

    RING-BASED NETWORK INTERCONNECT
    102.
    发明申请
    RING-BASED NETWORK INTERCONNECT 有权
    基于环的网络互连

    公开(公告)号：US20160173325A1

    公开(公告)日：2016-06-16

    申请号：US14567143

    申请日：2014-12-11

    Applicant: ELBIT SYSTEMS OF AMERICA, LLC

    Inventor： Robert A. Woodward ,  Daniel M. Herring ,  Andrew W. Hull

    IPC: H04L12/24

    CPC classification number: H04L41/0803 ,  H04L12/4625 ,  H04L41/0663 ,  H04L41/12

    Abstract: A network. At least some embodiments are a network including a first root node connected to a first port of a first switch and a second root node connected to a first port of a second switch. A first link is connected to a second port of the first switch and connected to a second port of the second switch. A second link is connected to a third port of a first switch and connected to a third port of the second switch.

    Abstract translation: 一个网络。 至少一些实施例是包括连接到第一交换机的第一端口的第一根节点和连接到第二交换机的第一端口的第二根节点的网络。 第一链路连接到第一交换机的第二端口并连接到第二交换机的第二端口。 第二链路连接到第一交换机的第三端口并连接到第二交换机的第三端口。

    SYSTEMS AND METHODS FOR NORTHFINDING
    103.
    发明申请
    SYSTEMS AND METHODS FOR NORTHFINDING 审中-公开
    用于加工的系统和方法

    公开(公告)号：US20160033272A1

    公开(公告)日：2016-02-04

    申请号：US14817688

    申请日：2015-08-04

    Applicant: ELBIT SYSTEMS OF AMERICA, LLC

    Inventor： Andrew STRUCKHOFF ,  Tom HARDY ,  Jason R. LANE ,  James SARETTE ,  Darius COAKLEY

    IPC: G01C19/38 ,  G01S17/87

    CPC classification number: G01S17/46 ,  G01C17/34 ,  G01C21/005 ,  G01C21/02 ,  G01S3/7861 ,  G01S3/7867 ,  G01S17/023 ,  G01S17/08

    Abstract: An apparatus for target location is disclosed. The apparatus includes a housing, which includes a range sensor to generate range data, an image sensor to generate image data, an inertial sensor to generate inertia data, and a processor. The processor is configured to receive the image data from the image sensor and determine a first orientation of the housing and receive the inertia data from the inertial sensor and modify the first orientation based on the inertia data to produce a modified orientation of the housing.

    Abstract translation: 公开了一种用于目标位置的装置。 该装置包括壳体，其包括用于生成范围数据的距离传感器，用于生成图像数据的图像传感器，用于产生惯性数据的惯性传感器和处理器。 处理器被配置为从图像传感器接收图像数据并且确定壳体的第一取向并且接收来自惯性传感器的惯性数据，并且基于惯性数据修改第一取向以产生壳体的修改的取向。

    MIMO SLOTTED ALOHA (MSA) SYSTEM
    104.
    发明申请
    MIMO SLOTTED ALOHA (MSA) SYSTEM 有权
    MIMO SLOTTED ALOHA（MSA）系统

    公开(公告)号：US20140016626A1

    公开(公告)日：2014-01-16

    申请号：US14029966

    申请日：2013-09-18

    Applicant: ELBIT SYSTEMS OF AMERICA, LLC

    Inventor： Qingyuan Dai ,  Charles H. Woloszynski

    IPC: H04W56/00

    CPC classification number: H04W56/001 ,  H04J3/0605 ,  H04L27/2656 ,  H04L27/2657

    Abstract: A method including receiving at a synchronizing node a first reference frame from a first reference node at a first time and storing a first time value representing the first time, and calculating a timing estimator by subtracting a minimum time value, representing the distance from the synchronizing node to the first reference node, from the first time value. The method includes receiving at the synchronizing node a second reference frame at a second time and transmitting from the synchronizing node to the first reference node a short tuning contention time frame. The method includes receiving at the synchronizing node from the first reference node an arrival time value representing the time at which the first reference node received the short timing contention frame and calculating a time drift from the first arrival time value and the second time value and adjusting the timing estimator based on the time drift.

    Abstract translation: 一种方法，包括在第一时间从第一参考节点在同步节点处接收第一参考帧并且存储表示第一时间的第一时间值，以及通过从表示距离的同步的距离中减去最小时间值来计算定时估计器 节点到第一个参考节点，从第一个时间值。 该方法包括在第二时间在同步节点处接收第二参考帧，并且从同步节点向第一参考节点发送短调谐争用时间帧。 该方法包括在第一参考节点的同步节点处接收表示第一参考节点接收到短定时竞争帧的时间的到达时间值，并从第一到达时间值和第二时间值计算时间漂移并调整 基于时间漂移的定时估计器。

    WAFER SCALE ENHANCED GAIN ELECTRON BOMBARDED CMOS IMAGER
    105.
    发明申请
    WAFER SCALE ENHANCED GAIN ELECTRON BOMBARDED CMOS IMAGER 有权

    公开(公告)号：US20250120193A1

    公开(公告)日：2025-04-10

    申请号：US18376674

    申请日：2023-10-04

    Applicant: Elbit Systems of America, LLC

    Inventor： Dan W. Chilcott ,  Arlynn W. Smith ,  John B. Hammond

    IPC: H01L27/146

    Abstract: An apparatus, system and method is provided for producing stacked wafers containing an array of image intensifiers that can be evacuated on a wafer scale. The wafer scale fabrication techniques, including bonding, evacuation, and compression sealing concurrently forms a plurality of EBCMOS imager anodes with design elements that enable high voltage operation with optional enhancement of additional gain via TMSE amplification. The TMSE amplification is preferably one or more multiplication semiconductor wafers of an array of EBD die placed between a photocathode within a photocathode wafer and an imager anode that is preferably an EBCMOS imager anode bonded to or integrated within an interconnect die within an interconnect wafer.

    Single Actuation Goggle Positioning Mounting Assembly
    107.
    发明申请
    Single Actuation Goggle Positioning Mounting Assembly 有权

    公开(公告)号：US20220197005A1

    公开(公告)日：2022-06-23

    申请号：US17690827

    申请日：2022-03-09

    Applicant: Elbit Systems of America, LLC

    Inventor： Victor Appel ,  John F. Kasper ,  David Alan Vogler ,  Keith D. Damick

    IPC: G02B23/12 ,  A42B3/04

    Abstract: A mounting device having a mounting assembly for mounting a pair of goggles to a helmet is provided. The mounting assembly is configured to provide at least three degrees of freedom of movement using one or more actuation mechanisms for locking and unlocking a position of the mounting device. The number of actuation mechanisms is less than a number of degrees of freedom. In some aspects, the number of actuation mechanisms is one. A rotation base connects the mounting assembly to the helmet, and a goggle linkage connects the mounting assembly to the goggles. Various single actuation mechanisms, including a sliding mechanism, a friction-based wire/brake mechanism, and a floating friction brake mechanism, are provided.

    WAFER SCALE ENHANCED GAIN ELECTRON BOMBARDED CMOS IMAGER
    108.
    发明申请
    WAFER SCALE ENHANCED GAIN ELECTRON BOMBARDED CMOS IMAGER 有权

    公开(公告)号：US20220037106A1

    公开(公告)日：2022-02-03

    申请号：US17377065

    申请日：2021-07-15

    Applicant: Elbit Systems of America, LLC

    Inventor： Dan W. Chilcott ,  Arlynn W. Smith ,  John B. Hammond

    IPC: H01J31/26 ,  H01J29/08 ,  H01J29/04

    Abstract: An apparatus, system and method is provided for producing stacked wafers containing an array of image intensifiers that can be evacuated on a wafer scale. The wafer scale fabrication techniques, including bonding, evacuation, and compression sealing concurrently forms a plurality of EBCMOS imager anodes with design elements that enable high voltage operation with optional enhancement of additional gain via TMSE amplification. The TMSE amplification is preferably one or more multiplication semiconductor wafers of an array of EBD die placed between a photocathode within a photocathode wafer and an imager anode that is preferably an EBCMOS imager anode bonded to or integrated within an interconnect die within an interconnect wafer.

    Landing zone designation system and method
    109.
    发明授权
    Landing zone designation system and method 有权

    公开(公告)号：US11164470B2

    公开(公告)日：2021-11-02

    申请号：US17033164

    申请日：2020-09-25

    Applicant: ELBIT SYSTEMS OF AMERICA, LLC

    Inventor： John G. Williams

    IPC: G08G5/00 ,  G08G5/02 ,  G08G5/06

    Abstract: A landing zone designation system is provided that includes a master and a slave landing strobes. A detector on an aircraft can detect master and slave optical signals, and a processor can be coupled to the detector to compute placement of the aircraft relative to the master and slave landing strobes. A method is provided for designating a landing zone for an aircraft. The method includes emitting first and second optical signals, where a determination is made whether the aircraft is to land at a first landing zone or a second landing zone depending on a difference between the first optical signal and the second optical signal. A distance to landing within the determined first landing zone or the second landing zone can also be determined.

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