Abstract:
A power amplifier (600, 700) integrated circuit, which generates an RF output signal by amplifying an RF input signal, includes a thermal-sensing circuit(620, 720), a feedback circuit(630, 730), a logic judging circuit(650, 750), an adjusting circuit(640, 740), and an amplifying circuit(OP1-OPn). The thermal-sensing circuit (620, 720) generates a thermal sensing signal according to the operational temperature, and the feedback circuit (630, 730) generates a power compensation signal according to power variations in the RF output signal. The logic judging circuit (650, 750) outputs a compensation signal according to the thermal sensing signal and the power compensation signal. The adjusting circuit (640, 740) adjusts the level of the RF input signal according to the compensation signal, thereby generating a corresponding 1st stage RF signal. The amplifying circuit(OP1-OPn) can amplify the 1st stage RF signal, thereby generating the corresponding RF output signal.
Abstract:
A voltage regulator (30) includes an amplifier (310), a power device (320), a delay signal generator (340), and a voltage-generating circuit (330). The amplifier (310) generates a control signal according to a reference voltage and a feedback voltage. The power device (320) generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator (340) generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit (330) provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.
Abstract:
A frequency calibration system includes at least two compensation circuits (204, 206) and a comparator. The at least two compensation circuits (204, 206) are coupled to an input signal for outputting at least a first compensation signal and a second compensation signal respectively. The comparator is coupled to the first compensation signal and the second compensation signal for outputting a calibration signal, where the calibration signal is used for determining an oscillation frequency of a crystal oscillator to achieve a purpose of frequency compensation with a temperature.
Abstract:
An antenna array method for enhancing signal transmission includes an antenna array (100,200,300) made of one or more series fed patch radiator sets (120,130,220,230,320), micro-strips (1401,1402,2401,2402,340_1-340_m) on one side of a base plate (110,210,310) and a metal layer (160,2601-2605,360_1-360_4) used for covering a block mapped by the micro-strips (1401,1402,2401,2402,340_1-340_m) to concentrate energy of radio signals emitted from radiator sets (120,130,220,230,320).
Abstract:
A voltage regulator (300) includes an output terminal (NOUT), a transistor (M1), a primary driving circuit (110), and a secondary driving circuit (320). The primary driving circuit (110) is coupled to a control terminal (GN) of the transistor (M1). The secondary driving circuit (320) is coupled between the control terminal (GN) of the transistor (M1) and a predetermined voltage terminal (VPRN). In a start-up mode, the transistor (M1) is driven by the primary driving circuit (110) and the secondary driving circuit (320), and the control terminal (GN) of the transistor (M1) and the predetermined voltage terminal (VPRN) are electrically coupled by the secondary driving circuit (320). In a normal mode, the transistor (M1) is driven by the primary driving circuit (110), and an electrical coupling between the control terminal (GN) of the transistor (M1) and the predetermined voltage terminal (VPRN) is disconnected by the secondary driving circuit (320).
Abstract:
An ultra-wideband radar transceiver and an operating method thereof are provided. The ultra-wideband radar transceiver includes a receiving module. The receiving module includes an I/Q signal generator, a first sensing circuit and a second sensing circuit. The I/Q signal generator receives M consecutive echo signals and generates M consecutive in-phase signals and M consecutive quadrature-phase signals accordingly, wherein M is an integer greater than 1. The first sensing circuit is coupled to the I/Q signal generator to receive the M consecutive in-phase signals and is configured to perform integration and analog-to-digital conversion on the M consecutive in-phase signals to generate a first digital data. The second sensing circuit is coupled to the I/Q signal generator to receive the M consecutive quadrature-phase signals and is configured to perform integration and analog-to-digital conversion on the M consecutive quadrature-phase signals to generate a second digital data.
Abstract:
An amplifier circuit (100) includes an output terminal (Po), an amplification unit (A1) and a switch (T3). The output terminal (Po) is used to output an amplification signal (Sa). The amplification unit (A1) includes a first transistor (T1) and a second transistor (T2). The first transistor (T1) includes a control terminal for receiving a first input signal (S1), a first terminal coupled to the output terminal (Po) for outputting an amplified first input signal, and a second terminal. The second transistor (T2) includes a control terminal for receiving a second input signal (S2), a first terminal coupled to the output terminal (Po) for outputting an amplified second input signal, and a second terminal. The switch (T3) includes a terminal coupled to the second terminal of the first transistor (T1). The amplification signal (Sa) is generated using at least the amplified first input signal and/or the amplified second input signal.
Abstract:
A control circuit (100) with a bypass function includes a first signal terminal (N1), a second signal terminal (N2), an output terminal (N opt ), a first switch unit (110) to a third switch unit (130), an output switch unit (150) and a bypass unit (180). The first signal terminal (N1) is used for receiving a first signal (S1). The second signal terminal (N2) is used for receiving a second signal (S2). The first switch unit (110) is coupled to the first signal terminal (N1). The second switch unit (120) is coupled between the first switch unit (110) and the output switch unit (150). The third switch unit (130) is coupled to the second signal terminal (N2). The output switch unit (150) is coupled between the second switch unit (120) and the output terminal (N opt ). The bypass unit (180) is coupled between the first switch unit (110) and the output terminal (N opt ).
Abstract:
A voltage control device (100) includes a charge pump (110), a driving circuit (120), and a control circuit (130). The charge pump (110) provides a first voltage (V1). The driving circuit (120) is coupled to the charge pump (110), and receives the first voltage (V1) and a reference voltage (VG). The driving circuit (120) outputs a driving signal (SIG OUT ) according to an input signal (SIG IN ), the first voltage (V1) and the reference voltage (VG). The control circuit (130) is coupled to the charge pump (110) and the driving circuit (120). Before the first voltage (V1) reaches a threshold level (THV1), the control circuit (130) adjusts the reference voltage (VG) to increase the voltage gap between the first voltage (V1) and the reference voltage (VG).