公开(公告)号：EP3910792A1

公开(公告)日：2021-11-17

申请号：EP21170616.3

申请日：2021-04-27

Applicant: RichWave Technology Corp.

Inventor： Huang, Pin-Yi ,  Chen, Chih-Sheng ,  Hsu, Ching-Wen

IPC: H03F3/193 ,  H03F1/56 ,  H03F1/32 ,  H03F3/21 ,  H03F1/22 ,  H03G3/00 ,  H03G1/00 ,  H03F3/72

Abstract: An amplifier circuit (1) includes an input terminal (10) to receive an input signal (RFin), an output terminal (12) to output an output signal (RFout), an amplification unit (14), and a phase adjustment unit (161 to 167). The amplification unit (14) includes an input terminal (IN) coupled to the input terminal (10) of the amplifier circuit (1), an output terminal (OUT) coupled to the output terminal (12) of the amplifier circuit (1), a first terminal (T1) coupled to a first voltage terminal (VDD), and a second terminal (T2) coupled to a second voltage terminal (GND). The phase adjustment unit (161 to 167) is coupled to the amplification unit (14). The amplifier circuit (1) can be operated in a plurality of modes to provide respective gains. The phase of the output signal (RFout) is maintained within a predetermined range regardless of the mode the amplifier circuit (1) is operated in.

公开(公告)号：EP3796561A1

公开(公告)日：2021-03-24

申请号：EP20193565.7

申请日：2020-08-31

Applicant: RichWave Technology Corp.

Inventor： Chien, Hwey-Ching ,  Chen, Chih-Sheng ,  Lin, Jhao-Yi ,  Hsu, Ching-Wen

IPC: H04B1/18

Abstract: The frequency detector (100) includes a first impedance circuit (110) and a second impedance circuit (120). The first impedance circuit (110) has a first terminal for receiving an input signal (SIG IN ), and a second terminal for outputting a divisional signal (SIG DVS ). The second impedance circuit (120) has a first terminal coupled to the second terminal of the first impedance circuit (110), and a second terminal coupled to a first system voltage terminal (NV1). The frequency response of the first impedance circuit (110) is different from a frequency response of the second impedance circuit (120). The resistance of the first impedance circuit (110), a resistance of the second impedance circuit (120), and the divisional signal (SIG DVS ) change with a frequency of the input signal (SIG IN ).

公开(公告)号：EP3633852A1

公开(公告)日：2020-04-08

申请号：EP19201028.8

申请日：2019-10-02

Applicant: RichWave Technology Corp.

Inventor： Chen, Chih-Sheng ,  Hsu, Ching-Wen

IPC: H03F1/02 ,  H03F1/22 ,  H03F3/21 ,  H03F3/72

Abstract: An amplifier circuit (100) includes an output terminal (Po), an amplification unit (A1) and a switch (T3). The output terminal (Po) is used to output an amplification signal (Sa). The amplification unit (A1) includes a first transistor (T1) and a second transistor (T2). The first transistor (T1) includes a control terminal for receiving a first input signal (S1), a first terminal coupled to the output terminal (Po) for outputting an amplified first input signal, and a second terminal. The second transistor (T2) includes a control terminal for receiving a second input signal (S2), a first terminal coupled to the output terminal (Po) for outputting an amplified second input signal, and a second terminal. The switch (T3) includes a terminal coupled to the second terminal of the first transistor (T1). The amplification signal (Sa) is generated using at least the amplified first input signal and/or the amplified second input signal.

公开(公告)号：EP3624337A1

公开(公告)日：2020-03-18

申请号：EP19192447.1

申请日：2019-08-20

Applicant: RichWave Technology Corp.

Inventor： Chen, Chih-Sheng ,  Lin, Jhao-Yi ,  Hsu, Ching-Wen

IPC: H03F3/72 ,  H03F1/56 ,  H03F3/193 ,  H03K17/00 ,  H03K17/693 ,  H04B1/00

Abstract: A control circuit (100) with a bypass function includes a first signal terminal (N1), a second signal terminal (N2), an output terminal (N opt ), a first switch unit (110) to a third switch unit (130), an output switch unit (150) and a bypass unit (180). The first signal terminal (N1) is used for receiving a first signal (S1). The second signal terminal (N2) is used for receiving a second signal (S2). The first switch unit (110) is coupled to the first signal terminal (N1). The second switch unit (120) is coupled between the first switch unit (110) and the output switch unit (150). The third switch unit (130) is coupled to the second signal terminal (N2). The output switch unit (150) is coupled between the second switch unit (120) and the output terminal (N opt ). The bypass unit (180) is coupled between the first switch unit (110) and the output terminal (N opt ).