PHASE MEASUREMENTS FOR HIGH ACCURACY DISTANCE MEASUREMENTS

    公开(公告)号:US20220174632A1

    公开(公告)日:2022-06-02

    申请号:US17107281

    申请日:2020-11-30

    Abstract: In at least one embodiment, a method for measuring a distance between a first communications device including a first local oscillator and a second communications device including a second local oscillator includes unwrapping N phase values to generate N unwrapped phase values. N is an integer greater than one. Each of the N phase values indicate an instantaneous phase of a received signal. The method includes averaging the N unwrapped phase values to generate an average phase value. The method includes wrapping the average phase value to generate a final phase measurement of the first local oscillator with respect to the second local oscillator.

    ADJUSTING DFT COEFFICIENTS TO COMPENSATE FOR FREQUENCY OFFSET DURING A SOUNDING SEQUENCE USED FOR FRACTIONAL TIME DETERMINATION

    公开(公告)号:US20220174453A1

    公开(公告)日:2022-06-02

    申请号:US17108908

    申请日:2020-12-01

    Abstract: A receiver includes a first discrete Fourier transform (DFT) block to perform a first single tone DFT on a positive tone associated with a sounding sequence. A second DFT block performs a second single tone DFT on a negative tone associated with the sounding sequence. A DFT coefficient generation block generates first DFT coefficients based on a nominal frequency of the positive tone and an estimated frequency offset between a transmitter frequency and a receiver frequency. The DFT coefficient generation block generates second DFT coefficients based on a nominal frequency of the negative tone and the estimated frequency offset. Multipliers in the DFT blocks multiply I and Q values of the sounding sequence with the coefficients. Accumulators in the DFT blocks accumulate multiplier outputs. An arctan function receives averaged accumulated values from the first and second DFT blocks and supplies first and second phase values used to calculate fractional timing.

    Data transmission between clock domains for circuits such as microcontrollers

    公开(公告)号:US11328755B2

    公开(公告)日:2022-05-10

    申请号:US16839329

    申请日:2020-04-03

    Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

    Radio frequency power amplifier adaptive digital pre-distortion

    公开(公告)号:US11316482B2

    公开(公告)日:2022-04-26

    申请号:US16904811

    申请日:2020-06-18

    Abstract: In an embodiment, an apparatus includes: a modulator to modulate a first signal; a distortion circuit coupled to the modulator to digitally pre-distort the first signal to compensate for a distortion of an amplifier; a distortion characterization circuit coupled to the distortion circuit to determine the distortion of the amplifier and configure the distortion circuit based on the determined distortion; a mixer coupled to the distortion circuit to upconvert the pre-distorted first signal to a pre-distorted radio frequency (RF) signal; and the amplifier coupled to the mixer to amplify the pre-distorted RF signal and output an amplified RF signal.

    DEMODULATOR FOR AN ISOLATION COMMUNICATION CHANNEL FOR DUAL COMMUNICATION

    公开(公告)号:US20220116250A1

    公开(公告)日:2022-04-14

    申请号:US17066242

    申请日:2020-10-08

    Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.

    SYSTEM AND METHOD OF LOW POWER SWITCH STATE DETECTION

    公开(公告)号:US20220074991A1

    公开(公告)日:2022-03-10

    申请号:US17100286

    申请日:2020-11-20

    Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.

    Frequency modulation tracking for band rejection to reduce dynamic range

    公开(公告)号:US11258643B1

    公开(公告)日:2022-02-22

    申请号:US17323782

    申请日:2021-05-18

    Abstract: In at least one embodiment of the invention, a method for reducing a dynamic range of a received radio frequency signal includes receiving digital IQ signals corresponding to an in-phase component of the received radio frequency signal and a quadrature component of the received radio frequency signal. The method includes demodulating the digital IQ signals to generate an instantaneous frequency signal. The method includes selecting a center frequency of a selectable filter according to whether an interfering signal is detected in a target frequency band of the received radio frequency signal. The center frequency is selected from a predetermined frequency and an estimated center frequency determined using the instantaneous frequency signal. The method includes filtering the digital IQ signals using the selectable filter configured using the center frequency to generate output digital IQ signals.

    Deglitcher circuit with integrated non-overlap function

    公开(公告)号:US11258432B1

    公开(公告)日:2022-02-22

    申请号:US17125561

    申请日:2020-12-17

    Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

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