公开(公告)号：US20210089329A1

公开(公告)日：2021-03-25

申请号：US17107183

申请日：2020-11-30

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Roberto COLOMBO ,  Nicolas BERNARD GROSSIER ,  Giovanni DISIRIO ,  Lorenzo RE FIORENTIN

IPC: G06F9/448 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30 ,  G06F21/71 ,  G06F21/60

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

公开(公告)号：US10678726B2

公开(公告)日：2020-06-09

申请号：US16360229

申请日：2019-03-21

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GmbH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20190159369A1

公开(公告)日：2019-05-23

申请号：US16259442

申请日：2019-01-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Domenico Massimo Porto ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Sergio Lecce

IPC: H05K7/20 ,  H01L23/34

Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

公开(公告)号：US10257917B2

公开(公告)日：2019-04-09

申请号：US15957578

申请日：2018-04-19

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH

Inventor： Philippe Sirito-Olivier ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Fritz Burkhardt

IPC: B60Q3/80 ,  H05B39/02 ,  H05B33/08 ,  B60Q1/00 ,  H05B39/04

Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.

公开(公告)号：US20150208557A1

公开(公告)日：2015-07-23

申请号：US14595391

申请日：2015-01-13

Applicant: STMICROELECTRONICS S.r.I. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Domenico Massimo PORTO ,  Giovanni Luca TORRISI ,  Sergio LECCE ,  Manuel GAERTNER

IPC: H05K7/20

CPC classification number: H05K7/20945 ,  H01L23/34 ,  H01L2924/0002 ,  H03K2017/0806 ,  Y10T307/773 ,  H01L2924/00

Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

Abstract translation: 包括多结集成电路的电子功率器件的热控制过程可以包括限定第一和至少一个第二组接点，每个组包括一个第一和至少一个第二结，并且将热检测器与每个 组。 可以执行第一组控制，其检测代表由热检测器检测到的温度的组电信号，参考组关键热事件处理组电信号，当对应的组电信号检测到关键组时识别临界组 并且产生适合于相对于集成电路的剩余结点选择性地去激活所识别的关键组的第一和至少一个第二结的组去激活信号。

公开(公告)号：US08989724B2

公开(公告)日：2015-03-24

申请号：US13667469

申请日：2012-11-02

Applicant: STMicroelectronics Application GmbH

Inventor： Juergen Boehler

IPC: H04M3/00 ,  H04M3/42 ,  H04B7/00 ,  G06K7/10

CPC classification number: G06K7/10237

Abstract: An NFC controller analyzes incoming commands, by name, and decides, according a predefined name table, to which secure element the actual command and following commands are sent for processing.

Abstract translation: NFC控制器根据名称分析传入命令，并根据预定义的名称表决定实际命令和后续命令发送到哪个安全元素进行处理。

公开(公告)号：US12253562B2

公开(公告)日：2025-03-18

申请号：US18186624

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F1/24 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/14

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

公开(公告)号：US12066962B2

公开(公告)日：2024-08-20

申请号：US18309103

申请日：2023-04-28

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G05B19/042 ,  G06F9/54 ,  G06F11/07 ,  G06F11/10 ,  G06F13/40 ,  G06F13/42 ,  H04L12/40 ,  H04L12/403 ,  H03M13/09

CPC classification number: G06F13/362 ,  G05B19/042 ,  G06F9/542 ,  G06F11/0739 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1004 ,  G06F13/4068 ,  G06F13/4282 ,  H04L12/40006 ,  H04L12/40013 ,  H04L12/40078 ,  H04L12/403 ,  G05B2219/1215 ,  G05B2219/2231 ,  G05B2219/31179 ,  H03M13/09 ,  H04L2012/40215

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US11914499B2

公开(公告)日：2024-02-27

申请号：US17515212

申请日：2021-10-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant ,  Misaele Marletti ,  Alessandro Daolio

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3082 ,  G06F11/3466

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

公开(公告)号：US20240048405A1

公开(公告)日：2024-02-08

申请号：US18489590

申请日：2023-10-18

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics Design & Application S.R.O.

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/423 ,  H04L12/40169 ,  H04L2012/40215

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.