公开(公告)号：US20030081148A1

公开(公告)日：2003-05-01

申请号：US10283029

申请日：2002-10-29

Applicant: STMicroelectronics S.A.

Inventor： Diego Coste ,  Ilija Materic ,  Francois Besson ,  Herve Maffini

IPC: H04N005/08

CPC classification number: H04N5/10

Abstract: Successive values of a horizontal phase of a video signal are determined a predetermined integer number of video lines after the successive occurrences of vertical synchronization pulses. The successive values of a parity bit are updated according to the successive values of the horizontal phase. Indications on the parity of the fields are provided from the successive values of the parity bit.

Abstract translation: 在连续出现的垂直同步脉冲之后，视频信号的水平相位的连续值被确定为预定的整数个视频行。 根据水平相位的连续值更新奇偶校验位的连续值。 字段奇偶校验的指示是从奇偶校验位的连续值提供的。

公开(公告)号：US20030062964A1

公开(公告)日：2003-04-03

申请号：US10232954

申请日：2002-08-29

Applicant: STMicroelectronics S.A.

Inventor： Yannick Guedon ,  Philippe Maige

IPC: H03K007/08

CPC classification number: H03K7/08 ,  H03K5/26 ,  H03L7/099 ,  H03L2207/06

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract translation: 用于产生脉宽调制信号的电路包括具有占空比不敏感相位比较器和适用于提供PLL的压控振荡器功能的Σ-Δ脉宽调制电路的锁相环（PLL） 。 因此，所生成的信号的频率由PLL同步到同步信号的指定频率，因此与占空比无关。

公开(公告)号：US20030042574A1

公开(公告)日：2003-03-06

申请号：US10236082

申请日：2002-09-06

Applicant: STMicroelectronics S.A.

Inventor： Thierry Schwartzmann

IPC: H01L027/082

CPC classification number: H01L29/0821

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract translation: 与在硅衬底中形成的第一导电类型的深区形成接触。 该接触包括第一导电类型的掺杂硅阱区域和连接在深层和阱之间的中间区域。 该中间连接区位于沟槽下方。 该制造方法能够形成垂直装置，特别是快速双极晶体管。

公开(公告)号：US20030006836A1

公开(公告)日：2003-01-09

申请号：US10124670

申请日：2002-04-17

Applicant: STMicroelectronics S.A.

Inventor： Bruno Pellat ,  Jean-Charles Grasset

IPC: G06G007/12

CPC classification number: H03F1/32 ,  H03F1/3211 ,  H03F2200/372

Abstract: A transconductance stage includes at least one principal bipolar transistor having a base linked to an input terminal, a collector linked to an output terminal, and an emitter linked to a supply terminal through a resistor. At least one bipolar compensation transistor is connected in parallel to the principal transistor and linked without going through the resistor to the supply terminal. The value RE of the resistance is chosen so that RE*I0>VT/2, where VT is the thermal voltage and I0 is the quiescent current of the principal transistor.

Abstract translation: 跨导级包括至少一个主要双极晶体管，其具有连接到输入端子的基极，连接到输出端子的集电极和通过电阻器连接到电源端子的发射极。 至少一个双极性补偿晶体管与主晶体管并联连接，而不通过电阻器连接到电源端子。 选择电阻的值RE，使得RE * I0> VT / 2，其中VT是热电压，I0是主晶体管的静态电流。

公开(公告)号：US20020186599A1

公开(公告)日：2002-12-12

申请号：US10139621

申请日：2002-05-06

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Sigrid Thomas ,  Cyrille Dray

IPC: G11C007/00

CPC classification number: G11C16/0416

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the output signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

Abstract translation: 具有基于单词的组织的非易失性存储器架构包括每个字的一个选择晶体管。 该选择晶体管用于由存储器单元的源选择单词。 以这种方式，可以通过使用低电压的地址解码器的输出信号直接进行选择。 独立于该选择，高电压切换到存储器单元的栅极和漏极。 这使得能够减少所需数量的高压开关。

公开(公告)号：US20020185589A1

公开(公告)日：2002-12-12

申请号：US10142262

申请日：2002-05-08

Applicant: STMicroelectronics S.A.

Inventor： Yvon Cazaux

IPC: H01L031/00

CPC classification number: B82Y20/00 ,  H01L27/1443 ,  H01L27/14609 ,  H01L27/14632 ,  H01L31/035245 ,  H01L31/03762 ,  H04N5/361 ,  Y02E10/548

Abstract: A photodetector including an amorphous silicon photodiode having its anode connected to a reference voltage, an initialization MOS transistor connected between the cathode of the photodiode and a first supply voltage to set the cathode to the first supply voltage during an initialization phase, and means for measuring the voltage of the photodiode cathode, including saturation means for bringing the photodiode cathode to a saturation voltage close to the reference voltage immediately before the initialization phase.

Abstract translation: 一种光电检测器，包括其阳极连接到参考电压的非晶硅光电二极管，连接在光电二极管的阴极之间的初始化MOS晶体管和在初始化阶段期间将阴极设置为第一电源电压的第一电源电压，以及用于测量 包括光电二极管阴极的电压，包括用于在初始化阶段之前使光电二极管阴极达到接近参考电压的饱和电压的饱和装置。

公开(公告)号：US20020176298A1

公开(公告)日：2002-11-28

申请号：US10117448

申请日：2002-04-05

Applicant: STMicroelectronics S.A.

Inventor： Sigrid Thomas ,  Leila Aitouarab

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C16/26

Abstract: In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.

Abstract translation: 在用于读取存储器单元的装置中，预充电电路连接到要读取的存储器单元和与要读取的存储器单元相关联的参考单元。 预充电电路将差分放大器的输出预充电到预定的电压电平。 读取装置还包括连接到差分放大器的输出的具有高阈值和低阈值的反相器。 预定的电压电平对应于高和低阈值之间的中间电平。

公开(公告)号：US20020171460A1

公开(公告)日：2002-11-21

申请号：US10101561

申请日：2002-03-19

Applicant: STMICROELECTRONICS S.A.

Inventor： Luc Garcia

IPC: H03B019/00

CPC classification number: H03D3/007

Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.

Abstract translation: 正弦信号乘法器电路基本上没有任何DC分量产生输出正弦信号。 该正弦信号乘法器电路包括在第一输入处接收第一正弦信号的第一乘法单元和第二输入端的第二正弦信号。 第一乘法单元传送第一输出信号。 正弦信号乘法器电路还包括与第一乘法单元相同的第二乘法单元，其在其第一输入处接收第二正弦信号，并在其第二输入端接收第一正弦信号，并传送第二输出信号。 正弦信号乘法器电路还包括加法器电路，用于将第一输出信号和第二输出信号相加，以从正弦信号乘法器电路提供基本上没有任何DC分量的输出信号。

公开(公告)号：US20020170743A1

公开(公告)日：2002-11-21

申请号：US10117463

申请日：2002-04-05

Applicant: STMicroelectronics S.A.

Inventor： Samuel Boret

IPC: H05K001/00

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01L23/5227 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductance device in monolithic structure is formed from a first metallization level layer of lower parallel conductive lines extending along the inductance pattern; next, on a second level, a set of vias is formed over each underlying conductive line being associated with at least two vias; and in a third metallization level, upper conductive lines interconnected to the underlying conductive lines by means of vias, the lower and upper conductive lines being shifted with respect to one another to ensure the electric continuity.

Abstract translation: 单片结构的电感器件由沿电感图形延伸的下并行导线的第一金属化层形成; 接下来，在第二级上，在与至少两个通孔相关联的每个下面的导电线上形成一组通孔; 并且在第三金属化水平中，通过通孔互连到下面的导电线的上导电线，下导电线和上导电线相对于彼此移位以确保电连续性。

公开(公告)号：US20020163832A1

公开(公告)日：2002-11-07

申请号：US10100511

申请日：2002-03-18

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

IPC: G11C011/34

CPC classification number: G11C16/12 ,  G11C16/0433

Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

Abstract translation: 电可编程和可擦除存储器包括连接到字线和排列成列的位线的存储器单元。 位线选择晶体管由位线选择信号驱动。 列选择锁存器各自包括用于列选择信号的锁定元件和用于传送取决于锁定元件的输出的门控制信号的电路。 每个列选择锁存器除了门控制信号之外还提供位线选择信号。 该信号至少在存储器单元的编程和读取阶段期间取决于锁定元件的输出。