公开(公告)号：US20020163832A1

公开(公告)日：2002-11-07

申请号：US10100511

申请日：2002-03-18

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

IPC: G11C011/34

CPC classification number: G11C16/12 ,  G11C16/0433

Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

Abstract translation: 电可编程和可擦除存储器包括连接到字线和排列成列的位线的存储器单元。 位线选择晶体管由位线选择信号驱动。 列选择锁存器各自包括用于列选择信号的锁定元件和用于传送取决于锁定元件的输出的门控制信号的电路。 每个列选择锁存器除了门控制信号之外还提供位线选择信号。 该信号至少在存储器单元的编程和读取阶段期间取决于锁定元件的输出。

公开(公告)号：US20020031015A1

公开(公告)日：2002-03-14

申请号：US09952904

申请日：2001-09-13

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  David Naura ,  Sebastien Zink

IPC: G11C005/00

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2pnull2q other data in the 2pnull2q llow-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2pnullqnull1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract translation: 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2P位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除字的所有单元; 2）在qp高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q低压锁存器（LV0，LV2，LV4，LV6）中加载2p-2q其他数据; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元; 以及重复2p-q-1次以下步骤：4）在步骤2）中加载2q高电压锁存器中的2q其他数据的2q高电压锁存器; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US20020126534A1

公开(公告)日：2002-09-12

申请号：US10096531

申请日：2002-03-11

Applicant: STMicroelectronics S.A.

Inventor： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC: G11C016/04

CPC classification number: G11C16/12

Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

Abstract translation: 电路产生用于擦除或编程存储器单元的电压。 电路包括电容器和连接到电容器的第一端子的放电电路。 放电电路包括第一晶体管，其漏极连接到电容器的第一端子。 当放电信号由第一晶体管的栅极接收时，第一晶体管激活放电电路。 放电电路包括缓慢放电臂和与第一晶体管的源极并联的快速放电臂。 放电电路产生低放电电流或高放电电流，用于根据工作模式选择信号放电电容器。

公开(公告)号：US20010017559A1

公开(公告)日：2001-08-30

申请号：US09742890

申请日：2000-12-21

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  Jean Devin

IPC: H03K005/12

CPC classification number: H03K17/163

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract translation: 集成电路被电压提供电压，并且包括具有由逻辑电路的输出驱动的栅极的输出MOS晶体管和用于偏置输出MOS晶体管的栅极的电路。 用于偏置栅极的电路被提供用于相对于否则将由逻辑电路的输出提供的栅极 - 源偏置电压降低导通状态下的输出MOS晶体管的栅极 - 源极偏置电压。 本发明特别适用于I2C总线的输出级。