公开(公告)号：KR1019940009427B1

公开(公告)日：1994-10-13

申请号：KR1019920003114

申请日：1992-02-27

Applicant: 삼성전자주식회사

Inventor： 박승권

IPC: G06F12/02

Abstract: The method generates control signal of address space changing inputted to address decoder not using software but only through hardware logic after processing 2 cycle behavior of CPU. The method comprises; output end of CPU connecing to address decoder and 2 stage flip flop, the end of address decoder connecting to EPROM and main bus controller, the end of 2 stage flip flop connecting to the address decoder.

Abstract translation: 该方法产生地址空间变化的控制信号，输入到地址解码器不使用软件，但只能通过硬件逻辑处理CPU的2个周期行为。 该方法包括： 输出端CPU连接地址解码器和2级触发器，地址解码器连接到EPROM和主总线控制器，结束2级触发器连接到地址解码器。