公开(公告)号：WO1996034455A1

公开(公告)日：1996-10-31

申请号：PCT/US1996005684

申请日：1996-04-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K03/01

CPC classification number: H03K4/48

Abstract: An asymmetrical ramp generator system (150) for a pulse width modulator includes a complementary clock circuit (152, 154); a first symmetrical dual ramp generator (156), responsive to the clock circuit, for generating first and second ramps (16, 30) having a predetermined voltage range and extending for a period equal to or greater than one half the clock cycle; a comparator device (158, 160), responsive to the first and second symmetrical ramps and ato a reference level (Level X) within the predetermined voltage range of the first and second ramps, for generating corresponing dual first and second asymmetrical drive signals (62, 64); and a second asymmetrical dual ramp generator (162, 164), responsive to the first and second asymmetrical drive signals, for generating third and fourth asymmetrical overlapping ramps which extend beyond the predetermined voltage range.

Abstract translation: 用于脉宽调制器的不对称斜坡发生器系统（150）包括互补时钟电路（152,154）; 响应于时钟电路的第一对称双斜坡发生器（156），用于产生具有预定电压范围并且延伸等于或大于时钟周期的一半的周期的第一和第二斜坡（16,30） 比较器装置（158,160），其响应于所述第一和第二对称斜坡，并且与所述第一和第二斜坡的预定电压范围内的参考电平（电平X）相对应，用于产生对应的第一和第二非对称驱动信号（62 ，64）; 以及响应于第一和第二不对称驱动信号的第二不对称双斜坡发生器（162,164），用于产生延伸超出预定电压范围的第三和第四不对称重叠斜坡。

公开(公告)号：WO1996028889A2

公开(公告)日：1996-09-19

申请号：PCT/US1996003205

申请日：1996-03-06

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WILSON, James ,  CELLINI, Ronald, A.

IPC: H03L07/113

CPC classification number: H03H17/0614 ,  H03H17/0657 ,  H03H17/0664 ,  H03L7/08 ,  H03L7/093 ,  H03L7/0992 ,  H03L2207/50 ,  H03M7/3022

Abstract: A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop. The method and apparatus thus locks to the phase and the frequency of the input signal and provide a phase-locked sigma-delta-modulated control signal.

Abstract translation: 一种用于相位锁定到输入信号并输出​​Σ-Δ调制控制信号的方法和装置。 本发明的方法和装置提供了一种Σ-Δ调制控制信号，其可由抽取器中的任何一个利用，以第一数据速率将数字数据以第二数据速率抽取数字数据，以及用于内插的内插器 以第一数据速率将数字数据以第二数据速率传送到数字数据。 抽头和内插器可用于模数转换器，数 - 模转换器和数 - 数转换器中的任何一个。 在一个实施例中，确定输入信号的周期并将其馈送到锁相环，该锁相环包括用于提供Σ-Δ调制控制信号的Σ-Δ调制器。 锁相环还包括用于确定输入信号和由锁相环产生的转换信号之间的相位和频差的相位检测器。 因此，该方法和装置锁定到输入信号的相位和频率，并提供锁相Σ-Δ调制控制信号。

公开(公告)号：WO1996017232A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015284

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  HOWE, Roger, T. ,  BART, Stephen

IPC: G01L01/14

CPC classification number: G01P15/125 ,  G01L1/148 ,  G01P15/131 ,  G01P2015/0814 ,  H01G5/14

Abstract: A micromachined force sensor containing separate sensing (38) and actuator (80) structures. A member (10) is suspended above the substrate so that it is movable along an axis (X) in response to a force. The member includes a set of parallel sense (38) fingers and a separate set of parallel force (80) fingers. The sense fingers are positioned between fingers of two sense plates (40, 42) to form a first differential capacitor, whose capacitance changes when the member moves in response to a force along the axis. The change in capacitance induces a sense signal on the member, which permits the measurement of the magnitude and duration of the force. The force fingers are positioned between fingers of two actuator plates (82, 84) to form a second differential capacitor. The sense signal can be used to provide feedback to the second differential capacitor to generate different electrostatic forces between the force fingers (80) and the two actuator plates (82, 84) to offset the force applied along the preferred axis. Limit stops (30) limit the movement of the member to less than the distance between the electrodes of the differential capacitors, to prevent contact between the electrodes. Additional fingers (100, 102, 104) are positioned around the differential capacitors to minimize parasitic capacitances.

Abstract translation: 包含单独的感测（38）和致动器（80）结构的微机械力传感器。 构件（10）悬挂在基板上方，使得其可以响应于力而沿轴线（X）移动。 该构件包括一组平行的手指（38）和一组单独的平行力（80）的手指。 感测指状物定位在两个感测板（40,42）的指状物之间，以形成第一差分电容器，当构件响应于沿着轴的力移动时，其电容发生变化。 电容的变化会引起元件上的感应信号，这样可以测量力的大小和持续时间。 力指定位于两个致动器板（82,84）的指状物之间，以形成第二差分电容器。 感测信号可以用于向第二差分电容器提供反馈以在力指（80）和两个致动器板（82,84）之间产生不同的静电力，以抵消沿着优选轴施加的力。 极限停止（30）将构件的移动限制为小于差动电容器的电极之间的距离，以防止电极之间的接触。 附加指状物（100,102,104）围绕差分电容器定位以最小化寄生电容。

公开(公告)号：WO1996010904A2

公开(公告)日：1996-04-18

申请号：PCT/US1995013386

申请日：1995-10-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas ,  YEE, Ronnin, J. ,  VALLEY, Mark, A. ,  COX, Steven, L. ,  GORIUS, Aaron, H.

IPC: G06F15/17 ,  G06F12/02 ,  G06F12/06 ,  G06F13/28 ,  G06F15/167 ,  G06F15/78 ,  G06F15/80 ,  G06F17/10

CPC classification number: G06F13/28 ,  G06F12/0284 ,  G06F15/7846 ,  G06F15/7857

Abstract: A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.

Abstract translation: 单片数字信号处理器包括用于执行数字信号计算的核心处理器，用于通过外部端口控制对数字信号处理器的外部访问的I / O处理器，用于存储用于数字信号的指令和数据的第一和第二存储体 计算以及互连核心处理器，I / O处理器和存储体的第一和第二总线。 核心处理器和I / O处理器访问第一个总线上的存储器，而不会对时钟周期的不同时钟相位产生干扰。 数字信号处理器的内部存储器和I / O处理器被分配给全局存储器空间的区域，这有助于多处理配置。 在多处理器系统中，每个数字信号处理器被分配处理器ID。 数字信号处理器包括总线仲裁电路，用于通过外部端口控制对外部总线的访问。 数字信号处理器可以包括一个或多个串行端口和用于与外部设备进行点对点通信的一个或多个链路端口。 DMA控制器通过外部端口，串行端口和链路端口控制DMA传输。

公开(公告)号：WO1996002943A1

公开(公告)日：1996-02-01

申请号：PCT/US1995009022

申请日：1995-07-17

Applicant: ANALOG DEVICES, INC. ,  MOORE, Thomas, D.

Inventor： ANALOG DEVICES, INC.

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated into standard integrated circuit (IC) packages is provided by increasing the thermal cross section between the leadframe paddle (22) and the lead fingers (leads) (26) so that the leads (26) are utilized for conducting a significant amount of heat away from the IC (21). A larger thermal cross section can be achieved by making the shape of the paddle perimeter (24) nonlinear to increase the surface area of its edge. In the preferred embodiment, the paddle perimeter (24) has a "serpentine" shape and the inner ends (28) of the leads (26) are placed in close proximity to the paddle perimeter (24) and are shaped to substantially follow its serpentine shape. The shaped paddle (22) and lead ends (28) increase the thermal cross section between the paddle (22) and the leads (26), resulting in improved thermal conduction. The leads (26) conduct the heat to the outside of the package, where it is dissipated into the circut board on which the leadframe package is mounted. For a package with a large number of leads, the paddle perimeter preferably has a saw-tooth shape, with at least some of the leads positioned between adjacent teeth.

Abstract translation: 通过增加引线框桨（22）和引线指（引线）（26）之间的热横截面来提供展现出改善的散热并且可以并入到标准集成电路（IC）封装中的引线框，使得引线 26）用于从IC（21）传出大量的热量。 可以通过使桨叶周边（24）的形状非线性地增加其边缘的表面积来实现更大的热横截面。 在优选实施例中，桨周边（24）具有“蛇形”形状，并且引线（26）的内端（28）被放置成紧邻桨叶周边（24）并且被成形为基本上跟随其蛇形 形状。 成形的桨叶（22）和引导端（28）增加了叶片（22）和引线（26）之间的热横截面，从而改善了热传导。 引线（26）将热量传导到封装的外部，并将其散发到安装有引线框封装的环形板中。 对于具有大量引线的封装，桨周边优选地具有锯齿形状，其中至少一些引线位于相邻的齿之间。

公开(公告)号：WO1995022117A1

公开(公告)日：1995-08-17

申请号：PCT/US1995001022

申请日：1995-01-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MACCARTNEY, Damien

IPC: G06G07/186

CPC classification number: G06G7/1865

Abstract: A switched-capacitor auto-zero integrator includes an integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge on the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval and a correction sub-interval. The sub-intervals occur only during the integrating interval such that the offset capacitor is charged by an offset voltage and a gain error voltage of the operational amplifier during the auto-zero sub-interval and the offset capacitor is connected to a summing node between the input capacitor and the integrating capacitor during the correction sub-interval.

Abstract translation: 开关电容器自动归零积分器包括积分器电路和校正电路。 积分器电路可以是包括具有输入线和输出线的运算放大器，耦合到由输入电压充电的输入电容器，耦合到输出线的积分电容器和可在一 积分时间间隔以将输入电容器连接到积分电容器，使得积分电容器被充电以补偿输入电容器上的电荷。 校正电路包括耦合到输入线的偏移电容器和可在自动零子区间和校正子间隔中操作的至少一个校正开关。 子间隔仅在积分间隔期间发生，使得偏移电容器在自动归零子区间期间由偏移电压和运算放大器的增益误差电压充电，并且偏移电容器连接到 输入电容器和积分电容器在校正子间隔期间。

公开(公告)号：WO1995008220A1

公开(公告)日：1995-03-23

申请号：PCT/US1994010268

申请日：1994-09-13

Applicant: ANALOG DEVICES, INC. ,  WILSON, James ,  CELLINI, Ronald, A. ,  SOBOL, James, M.

Inventor： ANALOG DEVICES, INC.

IPC: H03M01/12

CPC classification number: H03H17/06 ,  H03H17/0614 ,  H03H17/0628 ,  H03L7/08 ,  H03L7/093 ,  H03L7/0992 ,  H03L2207/50 ,  H03M3/498

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.

Abstract translation: 一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。 本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。 在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。 在另一个实施例中，数字数据以固定比例内插，然后在Σ-Δ调制频率选择信号的控制下被抽取，该Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。 使用第n级m位Σ-Δ调制器调制频率选择信号。 数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。 该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。

公开(公告)号：WO1993019523A1

公开(公告)日：1993-09-30

申请号：PCT/US1993002123

申请日：1993-03-08

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WURCER, Scott, A.

IPC: H03F03/45

CPC classification number: H03G1/0023 ,  H03F1/3211

Abstract: A distortion cancellation amplifier system, more particularly an operational amplifier system includes a current mirror circuit having an input, an output and a common terminal; a device for providing a pair of differential current signals to the input and output terminal of the current mirror circuit; a control device (30), responsive to said output terminal of the current mirror circuit, for controlling the voltage at the common terminal to drive the voltage at the input terminal of said current mirror circuit to track the voltage on the output terminal of the current mirror circuit; an output amplifier stage having a predetermined gain and having an input and an output terminal with its input terminal connected to the output terminal of the current mirror circuit; a gain control device (32) having a predetermined impedance connected with the input terminal of the output amplifier; and a distortion suppression device (36) connected between the output terminal of the output amplifier and the input terminal of the current mirror circuit and having an impedance equal to the predetermined impedance of the gain control device divided by the predetermined gain of the output amplifier for cancelling signal distortion introduced by the output amplifier stage.

公开(公告)号：WO1993018550A1

公开(公告)日：1993-09-16

申请号：PCT/US1993002135

申请日：1993-03-10

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BROKAW, A., Paul

IPC: H01L27/02

CPC classification number: H01L27/0248

Abstract: A circuit construction for biasing near a pocket containing a power supply potential circuit element in a junction-isolated circuit. In normal operation if the polarity of the supply voltage is reversed from that intended the pocket is disconnected. To achieve this, in one embodiment the emitter of a transistor is connected to the positive supply voltage. The collector of that transistor is used to bias the pocket, containing a circuit element, which in normal operation should receive the supply voltage. When the supply voltage is reversed, the emitter-base junction is reverse biased and the collector-base junction is turned off. The pocket is thus disconnected from the supply during supply reversal. The transistor may also have a second collector to handle reinjection of carriers when it is saturated. This second collector can be connected to the base or used by other circuits to detect when saturation occurs.

Abstract translation: 一种用于在接合隔离电路中偏置在包含电源电位电路元件的口袋附近的电路结构。 如果电源电压的极性与预期相反，那么在正常工作中，口袋断开。 为了实现这一点，在一个实施例中，晶体管的发射极连接到正电源电压。 该晶体管的集电极用于偏置包含电路元件的袋，其在正常操作中应该接收电源电压。 当电源电压反向时，发射极 - 基极结被反向偏置，并且集电极 - 基极结被断开。 因此，在供应反转期间，该口袋与电源断开。 当晶体管饱和时，晶体管也可以具有第二集电极以处理载流子的再注入。 该第二收集器可以连接到基座或由其他电路使用，以检测何时发生饱和。

公开(公告)号：WO1993016494A1

公开(公告)日：1993-08-19

申请号：PCT/US1993000816

申请日：1993-01-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ROBINSON, Derek, W. ,  KRIEGER, William, A. ,  MARTINEZ, Andre, M. ,  McDEVITT, Marion, R.

IPC: H01L27/06

CPC classification number: H01L21/8249

Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.

Abstract translation: 单个半导体衬底上的双极晶体管和MOS晶体管包括在衬底上沉积单层多晶硅，包括两种或两种类型的互补晶体管及其制造方法。 这些器件通过在衬底上沉积单层多晶硅并在每个双极发射极区域周围蚀刻以环形形式形成的狭缝，然后用绝缘氧化物填充该槽。 然后，形成发射体和非本征基区。 发射体与外部基极区域自对准。 可选的包层工艺产生硅化合物的表面层，低电阻导体。 所得到的结构产生了其中尺寸约束最小的高性能装置，并且可以在装置的顶表面处形成接触区域。