公开(公告)号：US20200328285A1

公开(公告)日：2020-10-15

申请号：US16849144

申请日：2020-04-15

Applicant: ASM IP Holding B.V.

Inventor： Suvi Haukka ,  Michael Givens ,  Eric Shero ,  Jerry Winkler ,  Petri Räisänen ,  Timo Asikainen ,  Chiyu Zhu ,  Jaakko Anttila

IPC: H01L29/49 ,  C23C16/455 ,  H01L21/285 ,  H01L21/3205 ,  C23C16/06 ,  C23C16/34

Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.

公开(公告)号：US20200312620A1

公开(公告)日：2020-10-01

申请号：US16881868

申请日：2020-05-22

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi Haukka ,  Marko Tuominen ,  Chiyu Zhu

IPC: H01J37/32 ,  C23F1/12 ,  H01L21/311 ,  C23G5/00 ,  H01L21/3213

Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

公开(公告)号：US10734497B2

公开(公告)日：2020-08-04

申请号：US16038024

申请日：2018-07-17

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/455 ,  H01L29/49 ,  C23C16/34

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

公开(公告)号：US20200227325A1

公开(公告)日：2020-07-16

申请号：US16834657

申请日：2020-03-30

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Chiyu Zhu ,  Kiran Shrestha ,  Pauline Calka ,  Oreste Madia ,  Jan Willem Maes ,  Michael Eugene Givens

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092

Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.

公开(公告)号：US10662533B2

公开(公告)日：2020-05-26

申请号：US16390385

申请日：2019-04-22

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi P. Haukka ,  Marko J. Tuominen ,  Chiyu Zhu

IPC: C23F4/02 ,  C23F1/12 ,  H01L21/3213 ,  C09K13/00 ,  H01L21/311 ,  C09K13/08 ,  C09K13/10 ,  H01J37/32 ,  H01L21/3065

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

公开(公告)号：US10541173B2

公开(公告)日：2020-01-21

申请号：US15836547

申请日：2017-12-08

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu

IPC: H01L21/768 ,  H01L21/02

Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

公开(公告)号：US20190244786A1

公开(公告)日：2019-08-08

申请号：US16390319

申请日：2019-04-22

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi P. Haukka ,  Marko J. Tuominen ,  Chiyu Zhu

IPC: H01J37/32 ,  C23F1/12 ,  H01L21/311 ,  C23G5/00

CPC classification number: H01J37/32009 ,  C23F1/12 ,  C23G5/00 ,  H01L21/31116 ,  H01L21/32135

Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

公开(公告)号：US10273584B2

公开(公告)日：2019-04-30

申请号：US15835212

申请日：2017-12-07

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi Haukka ,  Marko Tuominen ,  Chiyu Zhu

IPC: C23F4/02 ,  C23F1/12 ,  H01L21/3213 ,  C09K13/00 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/311

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

公开(公告)号：US20190067003A1

公开(公告)日：2019-02-28

申请号：US16105745

申请日：2018-08-20

Applicant: ASM IP Holding B.V.

Inventor： Bhushan Zope ,  Shankar Swaminathan ,  Kiran Shrestha ,  Chiyu Zhu ,  Henri Tuomas Antero Jussila ,  Qi Xie

IPC: H01L21/02 ,  H01L21/768

Abstract: Methods for depositing a molybdenum metal film directly on a dielectric material surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; and depositing a molybdenum metal film directly on the dielectric surface, wherein depositing comprises: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed directly on a surface of a dielectric material deposited by the methods of the disclosure are also disclosed.

公开(公告)号：US10211308B2

公开(公告)日：2019-02-19

申请号：US14919536

申请日：2015-10-21

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Timo Asikainen ,  Robert Brennan Milligan

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3205 ,  C23C16/04 ,  C23C16/32 ,  C23C16/455 ,  H01L21/28 ,  H01L29/78

Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.