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    ERROR INFORMATION TRANSFER SYSTEM
    101.
    发明专利
    ERROR INFORMATION TRANSFER SYSTEM 失效

    公开(公告)号：JPS57137917A

    公开(公告)日：1982-08-25

    申请号：JP2379581

    申请日：1981-02-20

    Applicant: FUJITSU LTD

    Inventor： SATOU MASAO ,  MITA TERUYOSHI ,  HOSHI FUMIO

    IPC: G06F12/16 ,  G06F11/07 ,  G06F11/30 ,  G06F13/00

    Abstract: PURPOSE:To use conventional interface control as it is without providing an additional wiring, by transferring error information by an information bus for sending and receiving information between a storage device and a peripheral equipment. CONSTITUTION:Error information is transferred by use of an information bus used for transferring data information between a storage device and a peripheral equipment. For instance, in case when an error is not detected in a read error information detecting circuit 1, information passes through AND circuits 8-0- 8-15 from the storage device 7 and is inputted to the peripheral equipment 3 through a bus line 4. Subsequently, in case when an error is detected in the read information, a detection error signal is sent out to AND circuits 10-0-10-2 and an OR circuit 11 by the error detecting circuit, and the polarity of terminals A, B of a controlling circuit 5 is converted to ''0'' and ''1'', respectively, by an output signal from the OR circuit 11. After that, the error detecting signal is entered into between the ''0'' bit and the second bit of the respective data buses, and the error information is sent out to the peripheral equipment 3.

    DATA HIGHWAY DEVICE
    102.
    发明专利
    DATA HIGHWAY DEVICE 失效

    公开(公告)号：JPS57111153A

    公开(公告)日：1982-07-10

    申请号：JP18680880

    申请日：1980-12-26

    Applicant: FUJITSU LTD

    Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI

    IPC: G06F13/00 ,  H04L12/40

    Abstract: PURPOSE:To raise the working efficiency of a transmission line, by providing a group code in addition to a regular address on a destination address part, and transferring a data by the 1 data plural address system. CONSTITUTION:A data from a transmission line 33 is divided into a clock component and a data component by a repeater 34, the clock component is sent to a timing generating circuit 38, necessary timing is generated, and as for the data component, a parallel signal is generated by a series-parallel register circuit 35. In this case, an address circuit 39 always monitors a destination address part DA of a buffer register 36. Also, on the destination address part DA, a group code part GAD showing a prescribed channel group in addition to a regular address part ADR, are provided, and a data is transferred to a specific channel of a station node, and a channel shown by the group code part GAD.

    DATA HIGHWAY SYSTEM
    103.
    发明专利
    DATA HIGHWAY SYSTEM 失效

    公开(公告)号：JPS56149850A

    公开(公告)日：1981-11-19

    申请号：JP5388580

    申请日：1980-04-23

    Applicant: FUJITSU LTD

    Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

    IPC: H04L7/00 ,  G06F13/00 ,  H04L12/437

    Abstract: PURPOSE:To make the maintenance and operation easy, by polling all the nodes from the highway supervisory unit by the use of the other system and detecting the node address, when a fault has occurred in one side of the duplex transmission line. CONSTITUTION:A looplike data highway system is formed by connecting a highway supervisory unit SV and station nodes ST0-STn to the transmission lines L0, L1 which are used in common for transmitting the data in the opposite direction mutually. In case step-out has occurred in the line L of one node ST, the supervisory unit SV executes the line switch operation to all the nodes by use of the system. After switching to the other system, the supervisory unit SV polls all the STs from this other system. The ST in which step-out has occured can be known by collecting a response to said polling by the supervisory unit SV and preparing a table.

    DATA HIGHWAY SYSTEM
    104.
    发明专利
    DATA HIGHWAY SYSTEM 失效

    公开(公告)号：JPS56137752A

    公开(公告)日：1981-10-27

    申请号：JP3986880

    申请日：1980-03-28

    Applicant: FUJITSU LTD

    Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

    IPC: H04L12/24 ,  H04L12/26

    Abstract: PURPOSE:To detect a station node where a fault is occurring by detecting whether the station node is used or not, by giving the address of the station node to a frame signal showing the in-no-use state, and by transmitting it to a loop monitoring device. CONSTITUTION:Response control circuit 11 detects the signal which shows the in- use state of a station, and a synchronizing signal and the signal showing the result of the detection of the in-use state of the station are inputted to timing signal generating circuit 5 and then inputted to multiplexer circuit 13 via responding circuit 6. Then, the output of circuit 13, while synchronizing with data signals stored in buffer registers 7-9, is included in the data signals as the station address of signal in out-of phase; and a serial signal is returned to transmission line L0 from repeater 1 via register 14 which converts a parallel signal into the serial signal.

    DATA COMMUNICATION SYSTEM
    105.
    发明专利
    DATA COMMUNICATION SYSTEM 失效

    公开(公告)号：JPS55153449A

    公开(公告)日：1980-11-29

    申请号：JP4746779

    申请日：1979-04-18

    Applicant: FUJITSU LTD

    Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

    IPC: H04L29/08 ,  G06F13/00 ,  H04L12/433

    Abstract: PURPOSE:To release the data transfer packet after data transfer and to make effective use of other communication control unit, by providing the control packet for inquiry/response in one frame. CONSTITUTION:In one frame information taking ahead the synchronizing pattern SYNC3, the inquiry/response control packets 5-0-5-3 (consisting of each field of control information, addressed address, transmission original address and response) together with the data transfer packets 4-0-4-2 are provided. When the communication control unit 2-0 of the data highway linked in ring shape communicates with the communication control unit 2-2 by using the packet 4-1, each address and electric message of the units 2-0 and 2-2 are written in the packet 4-1, the unit 2-2 acknowledges the address itself and receives the message, and next, any one response field of the control packet is used to inform the reception state to the unit 2-0, and the packet 4-1 is released in this stage, allowing to use for other communication control units.

    SELECTING COMMUNICATION SYSTEM FOR PLURAL PROCESSORS VIA COMMON INPUT*OUTPUT DEVICE
    106.
    发明专利
    SELECTING COMMUNICATION SYSTEM FOR PLURAL PROCESSORS VIA COMMON INPUT*OUTPUT DEVICE 失效

    公开(公告)号：JPS54102933A

    公开(公告)日：1979-08-13

    申请号：JP949678

    申请日：1978-01-31

    Applicant: FUJITSU LTD

    Inventor： SUZUKI YOUICHI ,  KUGIMIYA SETSUO ,  HANADA AKIO ,  MITA TERUYOSHI ,  NAKAMURA HIROSHI

    IPC: G06F13/14 ,  G06F3/00 ,  G06F15/16 ,  G06F15/177

    Abstract: PURPOSE:To perform the priority selection via the input/output device for the system in which one unit of the input/output device is shared by plural units of CPU, by providing the means which selects the remote CPU and memorizes the interruption to the input output device. CONSTITUTION:Input/output device IO turns on one bit in selection register 4 through program 4. Thus, one unit of CPU1-CPUn is selected, and the interruption is applied to the corresponding CPU when one bit in interruption memory register 5 corresponding to the selected CPU is turned off. Thus, the communication is carried out. No start request is accepted from CPU1-CPUn as long as register 5 is off. FF1 is set when IO is use to inform the busy state to all CPU's. As a result, the communication becomes impossible even though the IO is idle unless the interruption is applied to one CPU which is priority-selected from IO.

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