公开(公告)号：JPS60254242A

公开(公告)日：1985-12-14

申请号：JP10994884

申请日：1984-05-30

Applicant: FUJITSU LTD

Inventor： SATOU MASAO ,  KAWABEMOTO AKIRA ,  NISHIOKA JIYUNJI

IPC: H04L1/00 ,  G06F5/06 ,  G06F5/12 ,  G06F11/10 ,  G06F13/00

Abstract: PURPOSE:To apply easily a retrial function to the transfer of data by performing a data parity check when the transferred data is received and delivering a request for retransfer of data in case a parity error is detected. CONSTITUTION:A buffer device writes an error display ''1'' on the corresponding position of a buffer 10 when a parity error is detected with the received data. At the same time, the present contents of a write address register 12 on an address register 19 and preserved there. While the signals are transmitted via a control line 20 of a common bus 5 to give a request for retransmission of data to a device that actually transferred data. A gate 22 is controlled as soon as the retransmitted data is received by the bus 5. Therefore, the contents of an address holding register 19 are used as a write address to write both the received data and the parity check result to the buffer 10 like the ordinary reception. Here the transmission of data is performed again in case a parity error is detected again.

公开(公告)号：JPS5831433A

公开(公告)日：1983-02-24

申请号：JP12915281

申请日：1981-08-18

Applicant: FUJITSU LTD

Inventor： SATOU MASAO

IPC: G06F3/023 ,  G01S7/40 ,  G05B19/10

Abstract: PURPOSE:To precisely repeat the same operation many times by once storing a switching operation sequence to be repeated and reading out the sequence to reproduce. CONSTITUTION:An operation panel is provided with a write-read circuit 24 consisting of a memory 22, an address counter 24a, a register 24b, and a comparator 24c, a timer 26 and a switching circuit 28. Registers 30, 32 for temprally storing the outputs of a switch receiver 14 and a comparator 34 for comparing the contents of these registers 30, 32 are also mounted on the operation panel. The information on a switch group status are inputted to an electronic device 16 at the timing of the change of the information and the switching operation of the preceeding operation is automatically repeated also in the present operation.

公开(公告)号：JPS55134461A

公开(公告)日：1980-10-20

申请号：JP4179779

申请日：1979-04-06

Applicant: FUJITSU LTD

Inventor： SATOU MASAO ,  MITA TERUYOSHI ,  HOSHI FUMIO

IPC: G06F12/16 ,  G06F12/06 ,  G06F13/00 ,  G11C7/00

Abstract: PURPOSE:To make it possible to access an address designated by address information correctly, by constituting a system so that the memory part to be accessed may be determined on a basis of a mounting signal, a mounting position signal and address information. CONSTITUTION:It is assumed that a high-speed memory array board and a low- speed memory array board are mounted in high-speed memory mounting position 2-1 and mounting position 2-4 of low-speed memory mounting area 3 respectively. In case that the access address is included in addresses 0-128K, signal MCYA is turned on because signal MSUA is turned on, and timing control circuit 5 generates a signal required for access of the high-speed memory part to access the high-speed memory part. In case that the access address is included in addresses 128K-512K, the output of gate 6 becomes logical 1, and signal MSUB and signal YB are turned on. Circuit 5 generates a signal required for access of the low-speed memory part to access the low-speed memory part.

公开(公告)号：JPS55134455A

公开(公告)日：1980-10-20

申请号：JP4072179

申请日：1979-04-04

Applicant: FUJITSU LTD

Inventor： HOSHI FUMIO ,  MITA TERUYOSHI ,  SATOU MASAO

IPC: G06F11/10

Abstract: PURPOSE:To give a very simple constitution to a circuit by constituting the circuit so that a new parity bit can be obtained by the parity bit of a data processing circuit and data of a part of it. CONSTITUTION:Data group A is output from data processing circuit 1. Data a2 of this data group A is processed into data a3 by data processing circuit 3. Accompanied with this processing, new parity bit p2 is formed according to data a2 and parity bit p1 by parity forming circuit 7. In circuit 7, data a2 is transferred to exclusive OR circuit E1 for every bit, and bit P1 is transferred to exclusive OR circuit E2, and the output of circuit E1 is transferred to the other input of circuit E2. Consequently, since data a2 is 10 and bit P1 is 1 now, logic 1 is output from circuit E1, and logic 0 is output from circuit E2, and bit P2 becomes logic 0. Thus, parity bit P2 can be obtained with a very simple circuit.

公开(公告)号：JPS5492148A

公开(公告)日：1979-07-21

申请号：JP16045877

申请日：1977-12-29

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  HANADA AKIO ,  MITA TERUYOSHI ,  HOSHI FUMIO ,  SATOU MASAO

IPC: G06F7/00 ,  G06F9/46 ,  G06F13/00

Abstract: PURPOSE:To make it possible to use conventionally-designed programs and newly- designed programs after extension, which are mixed, by providing a program discriminating method and control operation changing method. CONSTITUTION:Bits received by line set 5-i are built up 4 into one character and an interruption is made to central controller 1. Next, controller 1 discriminates what line set the data come from to inform circuit connection device 4 of the address of memory unit 2 where data will be stored and then indicates channel adaptor 3 that when a fixed number of characters are built up, data are transmitted to the host computer. For example, when a data communication system is extended assuming that line sets before extension are 5-0 to 5-31 and extended ones are 5-32 and 5-33, interruptions to line sets 5-0 to 5-31 are processed by conventional programs before the extension, namely, BC-mode exclusive-use programs and interruptions to extended ones are processed by newly-designed, namely, EC-mode exclusive-use programs.

公开(公告)号：JPS60142452A

公开(公告)日：1985-07-27

申请号：JP25002683

申请日：1983-12-28

Applicant: FUJITSU LTD

Inventor： BABA YASUO ,  SATOU MASAO ,  KABEMOTO AKIRA

IPC: G06F12/14 ,  G06F21/02

Abstract: PURPOSE:To protect an area to be inhibited from writing of data precisely by setting up a flag bit for displaying whether data writing in said area is to be permited or not in accordance with the area having a fixed size. CONSTITUTION:When the IPL of a control program to a storage device 2 is ended, the end is informed to a flag writing control part 4 by a signal S and an address control part 1 generates an address in an area to be inhibited from writing. The data concerned are stored in a register 5. At that time, the control part 4 generates a flag, stores the flag in a flag setting part 6 and rewrites the flag on the formed address position in the storage device 2. Consequently, the flag is displayed in a flag display part 3 corresponding to the address concerned. After repeating said operation and ending the writing of all flags, the status is informed to the control program by a signal E and the system is opened. Then, the data writing to the storage device 2 is inhibited by the contents of a flag detecting part 7.

公开(公告)号：JPS60117364A

公开(公告)日：1985-06-24

申请号：JP22563383

申请日：1983-11-30

Applicant: FUJITSU LTD

Inventor： SATOU MASAO ,  BABA YASUO ,  KABEMOTO AKIRA

IPC: G06F13/38 ,  G06F13/12

Abstract: PURPOSE:To receive smoothly data from an I/O, by storing data from the I/O stored in a buffer memory through a common bus in a storage device in such a way that those having higher priorities of the I/O are preferentially stored. CONSTITUTION:Data on a common bus transferred from an I/O are written in a buffer memory by a writing circuit 13, but their addresses are detected and used by a priority detecting circuit 12 on a control bus. Priority information on the control bus is set in FFs 81-84 through a decoder 7. One having the highest priority is selected out of outputs of the FFs 81-84 by means of gates 91-94 and again converted into priority information (address of the buffer memory) by an encoder 10. Then the contents of the buffer memory of the address is read out and stored in a storage device 14 in the order of priority by a cycle steal. Therefore, data from the I/O can be received smoothly, even when an I/O to which high-speed processing of data is requested is connected.

公开(公告)号：JPS60117361A

公开(公告)日：1985-06-24

申请号：JP22563483

申请日：1983-11-30

Applicant: FUJITSU LTD

Inventor： KABEMOTO AKIRA ,  BABA YASUO ,  SATOU MASAO

IPC: G06F13/16

Abstract: PURPOSE:To omit a cache memory to increase the data transfer speed between a processor and a memory and to improve the data processing efficiency, by providing an exclusive bus and a system adaptor between the processor and the memory. CONSTITUTION:The access control to both memory 7 and processor 8 is performed collectively through an MS control part 19 in the processor 8. When the processor writes data to the memory 7, the data is transferred via a bus 14. While a bus 18 is used to read data out of the memory 7. Thus the data can be transferred at a high speed between the memory 7 and the processor 8 with use of exclusive buses 14 and 18. In case the data from an I/O is written, the data is transferred by a bus 13 via a system bus 11 and a system adaptor 10. When the data read out of the memory 7 is sent to the I/O, a bus 17 is used. In such a way, a cache memory can be omitted and attain the data processing at a high speed and with high efficiency.

公开(公告)号：JPS58166427A

公开(公告)日：1983-10-01

申请号：JP4940982

申请日：1982-03-27

Applicant: FUJITSU LTD

Inventor： SATOU MASAO ,  HOSHI FUMIO

IPC: G06F12/14 ,  G06F13/28 ,  G06F13/30

Abstract: PURPOSE:To simplify a cycle steal control circuit and to improve flexibility and versatility by using a storage protection address as both a cycle steal request signal and a cycle steal premit signal in common. CONSTITUTION:Peripheral devices 1A-1C are provided with comparing and selecting circuits 2A-2C and storage protection address generating circuits 3A- 3C respectively. For the storage protection address generating circuits 3A-3C, values corresponding to priority are set and storage protection addresses (PKA) corresponding to the priority are generated. The comparing and selecting circuits 2A-2C when the peripheral devices to which they belong send out cycle steal requests compare their PKAs with PKAs sent from other devices. Then, each comparing and selecting device outputs its PKA to a succeeding device when its PKA is greater, or the PKA sent from another device.

公开(公告)号：JPS57137917A

公开(公告)日：1982-08-25

申请号：JP2379581

申请日：1981-02-20

Applicant: FUJITSU LTD

Inventor： SATOU MASAO ,  MITA TERUYOSHI ,  HOSHI FUMIO

IPC: G06F12/16 ,  G06F11/07 ,  G06F11/30 ,  G06F13/00

Abstract: PURPOSE:To use conventional interface control as it is without providing an additional wiring, by transferring error information by an information bus for sending and receiving information between a storage device and a peripheral equipment. CONSTITUTION:Error information is transferred by use of an information bus used for transferring data information between a storage device and a peripheral equipment. For instance, in case when an error is not detected in a read error information detecting circuit 1, information passes through AND circuits 8-0- 8-15 from the storage device 7 and is inputted to the peripheral equipment 3 through a bus line 4. Subsequently, in case when an error is detected in the read information, a detection error signal is sent out to AND circuits 10-0-10-2 and an OR circuit 11 by the error detecting circuit, and the polarity of terminals A, B of a controlling circuit 5 is converted to ''0'' and ''1'', respectively, by an output signal from the OR circuit 11. After that, the error detecting signal is entered into between the ''0'' bit and the second bit of the respective data buses, and the error information is sent out to the peripheral equipment 3.